This work introduces the iSensMEX-POT platform, a potentiostat-based detection system for conducting cyclic voltammetry measurements. It consists of a mixed-mode application-specific integrated circuit (ASIC) and a user digital interface unit based on Raspberry/Python platform. The ASIC consists of three main building blocks: a potentiostat built by three operational amplifiers (OpAmps) working as an analog front-end, a 10-bit R2R digital-to-analog converter (DAC) and a 10-bit successive-approximation analog-to-digital converter (SAR-ADC) composing the mixed signal mode processing stage, and a digital finite state machine using the Inter-Integrated Circuit (I ² C) protocol conforming the digital data processing and transmission section. The Raspberry controls the ASIC using the I ² C, writes a digital words into the ASIC’s registers to replicate a triangular cyclic voltammetry signal with a scan rate of 200 mV/s over a range of ±1 V, and reads the digitized data from the SAR-ADC. The Raspberry platform displays the resulting waveform on a touch-screen using a graphical user interface (GUI). Also, a precision model based on the open-loop gain of the amplifier and an output noise quantification model were developed and applied to design a highly accurate potentiostat based on three amplifiers. The proposed platform’s functionality and accuracy was validated by comparing the data gathered by the iSensMex-POT with the data obtained with the EVAL-AD5940ELCZ commercial board. The proposed ASIC was mathematically modeled, simulated and fabricated in a 180 nm CMOS standard technology, featuring a silicon area of 1.39 mm ² and a power consumption of 52.99 mW (16.05 mA @ 3.3 V).

This work describes MexSIC, a data acquisition channel designed for Silicon Photomultipliers (SiPMs), composed of a mixed-mode application specific integrated circuit (ASIC) front-end, an FPGA-based processing stage, and a user interface. The ASIC provides a 1-bit sigma-delta modulated (ΣΔ – M ) digital equivalent of the input SiPM current, a flag indicating the start/end of the SiPM pulse, and a clock reference generated by an internal Phase Locked Loop (PLL). At the ASIC input stage, the SiPM current is converted to voltage by means of a 1.57 GHz bandwidth transimpedance amplifier (TIA), the gain of which can be switched between 21 dB and 48 dB, allowing for an input current range between 20 μ A and 20 mA. The generated voltage signal is then fed to a Triggering Unit (TU) implemented to discriminate between desired signals and the spurious ones, and in parallel, also to a second-order ΣΔ modulator providing 6.1 Equivalent Number Of Bits (ENOB). The TU circuit sends a start/end bit flag by comparing the SiPM voltage signal with an 8-bit programmable voltage reference. The ΣΔ was selected to have a single output line instead of using a data bus with many lines, which is important in applications where the number of SiPM channels being read out is very large. The 10 MHz bandwidth ΣΔ – M uses an Over Sampling Ratio (OSR) of 50, and a 1 GHz sampling clock that is generated by a PLL using an off-chip 100 MHz reference. The FPGA receives the ASIC ΣΔ modulated output signal and performs a decimation process by means of a Cascade Integrator Comb (CIC) filter to complete the data recovery. The recovered signal is visualized in a Matlab programmed Graphical User Interface (GUI). The MexSIC ASIC was designed in a 180 nm CMOS standard process using Cadence ^© software, and the processing stage was implemented in a Kintex-7 FPGA.