We present a collective PIC die-to-wafer dielectric bonding process, enabling SiN waveguide-based die-to-wafer evanescent couplers with insertion losses of 0.36 ±0.18dB at 1310nm wavelengths, paving the way to optically interconnected 300mm wafer-scale multi-chip compute systems.

We present 56-cm long LPCVD SiN waveguides traversing a full 300mm wafer, targeting future optically interconnected wafer-scale multi-chip compute systems. High-precision reticle stitching (loss below 0.01dB/interface) enables intra-wafer waveguide loss of just 0.15dB/cm in the O-band.

With the rapid development of artificial intelligence (AI) and machine learning (ML) applications, wafer-level optical I/O is becoming increasingly attractive for massive and efficient data interconnects in future wafer-scale multi-processor-units (multi-XPU) compute clusters with unparalleled data bandwidth, energy efficiency, and low latency. In this paper, we present a 300 mm sized wafer reticle-stitched low-pressure chemical vapor deposition (LPCVD) silicon nitride (SiN) waveguide technology and demonstrate a multi-reticle-stitched ~56 cm long waveguides across 20 reticles with propagation loss of 0.13~0.15 dB/cm at 1310 nm wavelength, and <0.001~0.002 dB SiN waveguide stitch loss, which is because of <5 nm high-precision reticle lithography offset. These advantageous features of low-loss reticle-stitched SiN waveguides have the potential to significantly enhance future optically interconnected wafer-scale multi-chip compute systems.

In this paper, we present a collective photonic integrated circuits (PIC) die-to-wafer dielectric bonding process, enabling silicon nitride (SiN) waveguide-based die-to-wafer evanescent coupling with insertion losses (IL) of 0.16 ±0.06 dB at optical O-band 1310 nm wavelength. This SiN evanescent coupling is of great significance and offers integration flexibility to effectively reduce optical coupling loss and enable higher-density optical connectivity compared to conventional edge coupling optical fiber arrays. The collective die-to-wafer bonding process enhances manufacturing efficiency by enabling high throughput, reducing handling steps, and lowering overall production costs. Besides, the evanescent coupling misalignment tolerance is up to 2 μm, which can mitigate alignment sensitivity and packaging difficulties. This advancement supports high-volume, low-latency, lower-energy-consumption optical I/O, paving the way for optically interconnected 300 mm wafer-scale multi-XPU compute systems for high-performance AI/ML computing.