Manual assembly of multi-pin cable harnesses remains vulnerable to miswiring when conductors are visually indistinguishable. This paper presents an industrial case study of a quick-connect harness composed of two connectors (receptacle-type and pin-type) linked by 16 black conductors (2.5 mm²; 200 mm length), where the dominant failure mode is a two-wire swap that breaks correct pin-to-pin mapping and may cause downstream equipment damage. In the baseline state, end-of-line verification relied on visual inspection only (1 min/unit), resulting in an internal nonconformity rate of 4% (repairable). To achieve the operational goal of zero defects (zero escapes), we propose and integrate an electronic pin-to-pin continuity and mapping fixture as a deterministic End-of-Line (EOL) quality gate implementing poka-yoke logic (“no PASS—no shipment”) and enabling structured traceability records. Using a before–after workload model that includes mandatory retest after rework, the fixture reduces test time to 0.33 min/unit. For a monthly volume of 1500 units, total quality workload (test + rework + retest) decreases from 31 h/month to 13.58 h/month, releasing 17.42 h/month. Global quality productivity increases from 48.39 units/h to 110.46 units/h (+128%). The proposed architecture couples deterministic electrical verification with data logging aligned to digital thread and data-driven quality management concepts to sustain continuous improvement and prevent customer escapes.

Manual assembly of multi-pin cable harnesses remains vulnerable to miswiring issues when conductors are visually indistinguishable. This paper presents an industrial case study of a quick-connect harness composed of two connectors (receptacle-type and pin-type) linked by 16 black conductors (2.5 mm² and 200 mm length), where the dominant failure mode is a two-wire swap that breaks correct pin-to-pin mapping and may cause downstream equipment damage. In the baseline state, end-of-line verification relies on visual inspection only (1 min/unit), resulting in an internal nonconformity rate of 4% (repairable). To achieve the operational goal of zero defects (zero escapes), we proposed and integrated an electronic pin-to-pin continuity and mapping fixture as a deterministic End-of-Line (EOL) quality-gate implementing poka-yoke logic (“no PASS—no shipment”) and enabling structured traceability records. Using a before–after workload model that includes a mandatory retest after rework, the fixture reduces test time to 0.33 min/unit. For a monthly volume of 1500 units, total quality workload (test + rework + retest) decreases from 31 h/month to 13.58 h/month, releasing 17.42 h/month. Global quality productivity increases from 48.39 units/h to 110.46 units/h (+128%). The proposed architecture couples deterministic electrical verification with data logging aligned to digital-thread and data-driven quality-management concepts to sustain continuous improvement and prevent customer escapes.