There have been significant advances regarding target detection in the autonomous vehicle context. To develop more robust systems that can overcome weather hazards as well as sensor problems, the sensor fusion approach is taking the lead in this context. Laser Imaging Detection and Ranging (LiDAR) and camera sensors are two of the most used sensors for this task since they can accurately provide important features such as target´s depth and shape. However, most of the current state-of-the-art target detection algorithms for autonomous cars do not take into consideration the hardware limitations of the vehicle such as the reduced computing power in comparison with Cloud servers as well as the reduced latency. In this work, we propose Edge Computing Tensor Processing Unit (TPU) devices as hardware support due to their computing capabilities for machine learning algorithms as well as their reduced power consumption. We developed an accurate and small target detection model for these devices. Our proposed Multi-Level Sensor Fusion model has been optimized for the network edge, specifically for the Google Coral TPU. As a result, high accuracy results are obtained while reducing the memory consumption as well as the latency of the system using the challenging KITTI dataset.

The aim of this work is to prove that it is possible to develop a system able to detect gestures based only on ultrasonic signals and Edge devices. A set of 7 gestures plus idle has been defined, being possible to combine them to increase the recognized gestures. In order to recognize them, Ultrasound transceivers will be used to detect the 2 dimensional gestures. The Edge device approach implies that the whole data is processed in the device at the network edge rather than depending on external devices or services such as Cloud Computing. The system presented in this paper has been proven to be able to measure Time of Flight (ToF) signals that can be used to recognize multiple gestures by the integration of two transceivers, with an accuracy between 84.18% and 98.4%. Due to the optimization of the preprocessing correlation technique to extract the ToF from the echo signals and our specific firmware design to enable the parallelization of concurrent processes, the system can be implemented as an Edge Device.

Sensor fusion is a critical aspect in autonomous drone navigation as several tasks, such as object detection and self-pose estimation, require combining information from heterogeneous sources. The performance of these solutions depends on several factors, such as the characteristics of the sensors and the environment, as well as the computing platforms, which can heavily impact their accuracy and response time. Carrying out such performance evaluations through real flight tests can be a resource-demanding, time-consuming, and, at times, risky process, which is why researchers often rely on simulation environments for testing and validating sensor fusion algorithms. The simulation environment should provide photorealistic environmental features, as well as a comprehensive set of sensors, in order to allow to test the most extensive set of sensor fusion algorithms. This paper presents AirLoop, an AirSim-based flight simulator for Hardware-in-the-Loop and Software-in-the-Loop algorithm testing and validation. AirLoop extends the sensor setup provided by AirSim with an FMCW RADAR sensor simulation, which has been evaluated based on the Infineon Technologies BGT60TR13C RADAR. Furthermore, this work provides several Software-in-the-Loop (SITL) and Hardware-in-the-Loop (HITL) demonstrations, including interfacing with the Pixhawk 2 flight controller and an extensive evaluation of the communication of the engine with the NVIDIA Jetson Nano, which has been evaluated in various use cases, including dataset creation, object detection, Path Planning, and Simultaneous Localization and Mapping (SLAM).

There is a growing interest in pushing computation to the edge, especially the problem-solving abilities of artificial neural networks (ANNs). This article presents a simplified method to obtain a ternary neural network based on the multilayer perceptron. The method is focused on resource-constrained devices, where memory, computing power, and battery are some of the most relevant constraints. A dynamic threshold is estimated to perform ternarization, and a new pruning technique is proposed to obtain a drastic reduction in the ANN’s size, with the corresponding decrease in resource utilization and power consumption of the resulting hardware. In addition, a support framework has been developed to automate hardware design exploration and generation from the network trained in software. Experimental results show that the proposed method and architecture, when implemented in a field-programmable gate array (FPGA), provide excellent figures in power (0.11–0.13 W) and efficiency (1225–1448 kfps/W) with respect to state of the art, being its efficiency double than the maximum one reported previously.

Distributed energy systems open up a vast field of research in power electronics. Local solar power generation requires DC-DC converters that adapt the energy generated by the panels to on-site distribution buses. In addition, the control of the power converter to obtain the maximum possible energy from the solar source is crucial for the correct deployment of these distributed grids. In this work, system-level solutions are proposed for this application as follows: On the one hand, the use of novel resonant forward-flyback converters allows for a higher energy density than that of a conventional flyback and more relaxed withstand voltages on the switching elements. On the other hand, the implementation of maximum power point tracking algorithms for solar energy using Edge AI enables the deployment of algorithms that maximize the energy obtained locally. These improvements are shown by means of a prototype demonstrator, using cutting-edge microcontrollers and the implementation of a DC-DC power converter based on the proposed topology.

This paper proposes a power-of-two-based quantization technique aimed at improving the hardware efficiency of artificial neural networks (ANNs) implemented on field-programmable gate arrays (FPGAs). The effectiveness of the proposed approach is validated using gated recurrent unit (GRU) models. The resulting architecture, referred to as $2^{Q}GRU$, exploits parallelism, optimized operation scheduling, and fine-grained data bit-width management to achieve efficient hardware realization. Compared with state-of-the-art FPGA implementations based on sparsity compression, $2^{Q}GRU$ demonstrates superior performance in terms of resource utilization and power consumption, while eliminating the need for dedicated DSP blocks. Furthermore, area and power efficiency can be further improved by trading latency for reduced hardware cost through an integrated implementation reduction strategy, enabling deployment on highly resource-constrained devices. Finally, the $2^{Q}GRU$ model is integrated into an automated ANN framework, allowing the proposed quantization and hardware optimization techniques to be readily extended to other ANN models and FPGA-based deployments.