This paper proposes a power-of-two-based quantization technique aimed at improving the hardware efficiency of artificial neural networks (ANNs) implemented on field-programmable gate arrays (FPGAs). The effectiveness of the proposed approach is validated using gated recurrent unit (GRU) models. The resulting architecture, referred to as $2^{Q}GRU$, exploits parallelism, optimized operation scheduling, and fine-grained data bit-width management to achieve efficient hardware realization. Compared with state-of-the-art FPGA implementations based on sparsity compression, $2^{Q}GRU$ demonstrates superior performance in terms of resource utilization and power consumption, while eliminating the need for dedicated DSP blocks. Furthermore, area and power efficiency can be further improved by trading latency for reduced hardware cost through an integrated implementation reduction strategy, enabling deployment on highly resource-constrained devices. Finally, the $2^{Q}GRU$ model is integrated into an automated ANN framework, allowing the proposed quantization and hardware optimization techniques to be readily extended to other ANN models and FPGA-based deployments.