As application conditions become increasingly demanding and usage becomes more aggressive, the performance of traditional insulated gate bipolar transistor (IGBT) and fast recovery diode (FRD) systems can no longer meet the required specifications. In these systems, FRDs are required to carry load current and allow current to return from the load to the IGBTs. Consequently, the reverse recovery performance of the FRDs significantly restricts the overall efficiency of the system. Therefore, how to predict the reverse recovery characteristics of the FRDs with greater precision has attracted considerable attention. In this context, this paper presents an in-depth investigation of the high-level injection carrier distribution and reverse recovery characteristics of punchthrough P-I-N (PT-PIN) FRD with a buffer layer. Specifically, the research explores the physical properties of the materials, doping concentrations, and the geometric structure of the devices. Furthermore, it takes into account the complex interactions among carrier recombination, diffusion, and drift, leading to the development of a model that delineates the spatial distribution of carriers and their influence on current conduction. Building upon the traditional step-wise analysis method, subsequently, the temporal aspects of the FRDs reverse recovery process were further segmented. Utilizing the derived carrier distribution model, a reverse recovery analytical model was constructed. The model was validated using a 1200 V, 100 A IGBT with 1200 V, 60 A FRD configured in a reverse parallel arrangement, which demonstrated a 5% improvement in prediction accuracy of V_R compared with previous models that employed the lumped charge method. Finally, a range of experiments with varying R_G, V_CC and I_F confirmed the broad applicability of this analytical model.

Insulated-gate bipolar transistor (IGBT) power modules suffer efficiency degradation at elevated operating junction temperatures. The thermal sensitivity of the collector–emitter saturation voltage (V_CEsat) induces thermal stress imbalance, constraining system efficiency and reliability. A multi-resistor cascade network model for carrier-storage trench-gate IGBTs (CS-IGBTs) is established. The simulation results agree with the measurements within 10% error. The model decomposes the temperature coefficient contributions of individual structural regions. Analysis reveals that the drift region resistance dominates the V_CEsat temperature coefficient. Based on this finding, a co-doping strategy is proposed through simultaneously increasing the doping concentration in the carrier-storage layer and P⁺ collector. This approach reduces the temperature sensitivity of carrier mobility in the drift region, thereby optimizing V_CEsat’s temperature sensitivity. For the fabricated 1200 V/40 A CS-IGBT, the V_CEsat temperature coefficient decreases from 2.38 mV/K to 1.76 mV/K over 300 K to 450 K, which represents a 25.4% reduction. The total switching loss at 450 K decreases from 9.32 mJ to 8.70 mJ, achieving a 6.7% improvement. This device-level optimization suppresses V_CEsat’s temperature sensitivity and switching losses, enhancing efficiency in high-temperature power module applications.