Fadjar Rahino Triputra

Dr. Fadjar Rahino Triputra

orcid

Research Focus & Metrics

Academic Career Length

4Years (2023-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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1 January 2025 in Indonesian Journal of Electrical Engineering and Computer Science
Verified
Journal Article
Open access
PDF file
YGYomi Guno
Yomi Guno
TATrio Adiono
Trio Adiono
JSJoko Suryana
Joko Suryana
FTFadjar Rahino Triputra
Fadjar Rahino Triputra
AHAsyaraf Hidayat
Asyaraf Hidayat
SOSiti Vivi Octaviany
Siti Vivi Octaviany
The variation in the k-factor value significantly influences the performance of unmanned aerial vehicle (UAV) air-to-ground point-to-point line of sight (A2G PTP LOS) communications over a Rician channel at 1,800 MHz using quadrature phase shift keying (QPSK) modulation and orthogonal frequency division multiplexing (OFDM) techniques. The research emphasizes the impact of the k-factor, which quantifies the dominance of the line-of-sight component over multipath scattering. The variation in the k-factor significantly influences UAV A2G PTP LOS communication performance for the empirical model (EM), as it involves precise measurements of the received power level in dBm from UAV to ground control station (GCS) across varying distances and altitudes. We introduce a method to compute the k-factor by assessing the ratio of the line-of-sight signal power to the multipath signal power, thereby enhancing channel modeling accuracy. Empirical analysis shows a strong correlation between bit error rate (BER) and signal-to-noise ratio (SNR) with differing k-factor values; a higher k-factor of 16.3 markedly improves performance, virtually eliminating errors at a 10 dB SNR, while a lower k-factor of 2.39 still shows significant errors at a 30 dB SNR. These results highlight the necessity of optimizing the k-factor in UAV A2G PTP LOS systems to ensure stable and reliable communication under diverse operational conditions.

29 June 2026 in Journal of King Saud University Computer and Information Sciences
Verified
Journal Article
Open access
PDF file
ALAndriani Adi Lestari
Andriani Adi Lestari
SMSuryadi MT
Suryadi MT
Kalamullah RamliKalamullah Ramli
Kalamullah Ramli
Teddy Surya GunawanTeddy Surya Gunawan
Teddy Surya Gunawan
EAEsti Rahmawati Agustina
Esti Rahmawati Agustina
FTFadjar Rahino Triputra
Fadjar Rahino Triputra
Many deployed internet of things (IoT) devices used for medical sensor logging, industrial telemetry, and smart metering require block-cipher-based random-access encrypted storage on 8-bit microcontrollers. Conventional 128-bit block ciphers impose significant flash and random-access memory (RAM) overhead on 8-bit platforms, introducing up to 100% padding overhead for short sensor records, while modern authenticated encryption with associated data (AEAD) schemes built from sponge permutations do not support constant-time random-access decryption due to their sequential structure. This work introduces SHOT (Substitution-rotation Hybrid Optimized Transform), an 80-bit block cipher tailored for 8-bit devices and co-designed with the storage format. SHOT integrates a 5-bit nonlinear substitution layer (S-box) and a linear layer inspired by the Ascon permutation into a 32-round Feistel network with a 160-bit key, enabling standard cipher block chaining (CBC) and counter (CTR) modes. Mixed-integer linear programming (MILP) analysis indicates estimated security margins of 17 and 20 rounds for differential and linear cryptanalysis, respectively, within our search limits. A fully unrolled SHOT assembly implementation on an AVR-class microcontroller achieves 384.7 cycles per byte and an energy cost of 330.6 nJ per bit, while a compact field-programmable gate array (FPGA) design sustains 251 Mbps using about 1,013 lookup tables. In a continuous glucose monitoring scenario, SHOT reduces padding overhead for per-record encryption and extends flash logging capacity on the same hardware partition.

11 December 2023
Verified
Conference Paper
Closed access
FTFadjar Rahino Triputra
Fadjar Rahino Triputra
RFRifki Firdaus
Rifki Firdaus
ITIrfansyah Yudhi Tanasa
Irfansyah Yudhi Tanasa
YGYomi Guno
Yomi Guno
FKFrandi Adi Kaharjito
Frandi Adi Kaharjito
MDMohamad Dahsyat
Mohamad Dahsyat
Using a low-cost, small-size, fully functional FPGA board as a flight control computer (FCC) remains challenging when flying UAV s. The superior flexibility of configuring digital circuits in an FPGA is believed to increase the efficiency of every process required, from reading sensors and carrying out high-speed data communications to moving actuators. This paper shows a way to explain an FPGA digital circuit design description for a UAV FCC minimum system for flying a fixed-wing UAV, i.e., a pilot-in-Ioop system. The field test verification of the proposed design shows that no 50 Hz PWM data to drive actuators is lost from PPM data transmitted, wrapped in a 39-byte data protocol when the UAV is flown. Therefore, the pilot behavior when flying the aircraft can be recorded, which shows the intensity of the aileron and elevator movements.