Three-phase bearingless induction motor is a multivariable, nonlinear and strong coupling object, to achieve its decoupling control with high performance, an inverse system decoupling control strategy based on air gap flux orientation is proposed. Under the conditions of air gap flux orientation of torque system, the stator currents of torque winding and suspension winding are taken as input variables, and the inverse system mathematical model of bearingless induction motor is established; adopting the inverse system method, the bearingless induction motor is decoupled into four pseudo linear subsystems, include motor speed first-order integral subsystem, air gap flux-linkage first-order integral subsystem, α and β displacement components second-order integral subsystems. The structure of decoupling control system is presented also. From the simulation results, it is clear that not only the air gap flux-linkage of torque system can be controlled accurately and directly, but also the dynamic decoupling control between motor speed, air gap flux-linkage of torque system and two radial displacement components can be achieved; Meanwhile, the control system has the characteristics of small overshoot and fast response speed.

Power efficiency for license plate recognition (LPR) under unconstrained scenarios is a crucial factor in many edge-based real-world applications, e.g., autonomous vehicles whose power budget is limited. While a bulk of prior works have explored LPR approaches for unconstrained situations on CPU and GPU servers, these methods result in huge power dissipation, and are ineffective in challenging scenes. In this work, we present a mixed-precision (MP) Transformer hardware architecture to meet the requirements of power efficiency and satisfactory LPR accuracy in unconstrained scenarios, dedicated to implementing power-efficient edge accelerators for difficult LPR tasks. Firstly, MP-LPR Transformer model is proposed, where novel mixed-precision quantization and non-linear approximation techniques are tailored for low bit-width inference. Secondly, vector tiling systolic array Transformer architecture (VTSATA) is proposed with unique vector tiling systolic array (VTSA) and vector ALU (VALU) designs, where VTSA is used to accelerate matrix multiplications, and VALU is used to process non-linear operations. Finally, a FPGA accelerator prototype based on our approach is developed. Experimental results demonstrate that our hardware platform can reduce power consumption more than $20\times$ compared to GPU platforms, and for challenge subset on CCPD dataset, our method can further improve nearly $1\%$ accuracy with respect to the state-of-the-art performance.

Conventional Image Signal Processors (ISPs) employ manually crafted designs with limited adaptability, resulting in suboptimal performance in dynamic environments for both visual quality and machine vision applications. While deep learning facilitates adaptive AI-ISPs, supervised approaches encounter domain shift limitations and substantial computational demands that impede edge deployment. This work introduces an adaptive zero-shot AI-ISP that dynamically optimizes processing pipelines without requiring paired training data. The proposed architecture implements dual specialized subnetworks for illumination estimation and denoising enhancement, operating collaboratively under Retinex theory principles to achieve boundary-aware illumination mapping and noise-resilient image restoration. Additionally, a physically constrained loss function is introduced to enhance color fidelity and noise suppression. For practical implementation, an FPGA-accelerated computing engine replaces transposed convolution with optimized bilinear interpolation, effectively eliminating artifacting while achieving superior memory efficiency through customized buffering architectures. A comprehensive evaluation demonstrates highly competitive performance, achieving a PSNR of 19.91/16.62 and an SSIM of 0.591/0.475 on LSRW-Huawei/Nikon datasets, alongside NIQE scores of 2.065/3.025 on DCIM and TM-DIED datasets. The hardware implementation attains 42.5 GOPS/W power efficiency, representing 35.4× and 7.3× improvements over conventional CPU and GPU platforms, establishing a comprehensive edge deployment solution for next-generation intelligent image processing systems.

The huge computational complexity and memory requirement of deep neural networks (DNNs) impede their deployability on resource-constrained edge-computing devices. To tackle this challenge, numerous model compression solutions have emerged, where Power-of-Two (PoT) quantization scheme demonstrates its potential in reducing computational complexity with complex multiplications replaced by bit-shifting arithmetic operations. However, most of existing methods resort to using full-precision hyper-parameters to avoid significant accuracy degradation, and so they achieve sub-optimal performance on the reduction of computation and memory cost. Therefore, we propose a novel efficient inference approach for resource-limited embedded devices. In our approach, integer-only PoT quantization scheme is designed to quantize both weights and activations into only PoT representations with fewer bit-width to achieve bit-wise inference. Additionally, a distribution-loss regularizer is developed to minimize the retraining disturbation introduced by quantizer. Furthermore, output weights are efficiently encoded in binary format by a two-stage compression pipeline. Finally, comprehensive experiments are conducted with different models and datasets. Experimental results indicate that our approach outperforms state-of-the-art approaches in terms of accuracy and compression rate, with more than 2 × the compression ratio previous methods achieve and 1.2 × accuracy improvement, under 3-bit precision with ResNet56.