With the rapid development of the Internet of Things (IoT), device and data security has attracted huge academic attention in recent years since conventional security methods are barely feasible in IoT circumstances. Traditional encryption methods require extensive computation complexity, which requires several hardware resources and power consumption. Meanwhile, due to the low power requirement, most IoT devices are lightweight with limited computing and storage capabilities. The dilemma leads to the need for a lightweight encryption method with decent data protection strength. Chaotic encryption can be applied in the IoT because of the characteristics of determinacy and strong randomness. However, its safety and hardware overhead are positively correlated with implementation precision. Therefore, this paper performs a quantitative analysis of the system under different precision conditions. Then, a hybrid chaotic encryption scheme with dynamic precision is proposed, which balances power consumption and security protection level. Finally, the proposed design is implemented by Verilog and synthesized using SMIC 65nm CMOS technology. The evaluation results proved that the proposed ASIC provides decent encryption strength under diverse precision, effectively overcoming the influence of limited precision with low hardware resources and power consumption.

Sparse code multiple access (SCMA) is a promising multiple access technology candidate for the next-generation communication system, which can dramatically improve spectral efficiency. However, the major challenge of SCMA is the very high detection complexity. Stochastic computing is a new number representation, which can carry out complex computations with very simple logics. In this paper, we extend the application of stochastic computing to SCMA detection and propose a low complexity stochastic SCMA detector. We also design three novel stochastic logic architectures: a new low hardware cost bit stream generation architecture, a low hardware cost stochastic function node update architecture and a fast converging stochastic variable node update architecture. Analysis and simulation results show that the proposed stochastic SCMA detector saves 69% complexity compared with the traditional SCMA detectors with a comparable bit error rate performance. The synthesis results with SIMC 65-nm CMOS technology show that the proposed stochastic SCMA detector achieves 640 Mbps total system throughput with only 1.45-mm $^{{{2}}}$ cell area.

Polar codes have received recent attention due to their potential to be applied in advanced wireless communication protocols such as the fifth generation mobile communication system (5G). Among the existing decoding algorithms, Belief Propagation (BP) exhibits high-throughput, low-latency, and soft output with a high hardware cost. Stochastic computing, as a form of approximate computing, provides a potential low-cost implementation solution for the BP algorithm. However, existing stochastic BP decoders suffer from a relatively long decoding latency resulting in low hardware efficiency. In this paper, a novel bit-wise iterative stochastic decoding architecture for the BP algorithm is proposed to improve the throughput and hardware efficiency. By utilizing the frozen bits of polar codes and stochastic computing, multiple novel optimization methods are presented to further speed up convergence and increase the hardware efficiency.

Sparse Code Multiple Access (SCMA) is a promising candidate multiple access technology for the fifth generation (5G) mobile communication system. In this paper, we propose a factor graph based high performance Joint Detection and Decoding scheme (JDD) for the Low Density Parity Check code (LDPC) coded SCMA system. Also, we propose a message damping aided reduced complexity JDD scheme (RC-JDD) to achieve a lower complexity. According to the simulation results, the proposed JDD scheme has 2.6dB Bit Error Rate (BER) performance gain compared with the traditional methods and approximates to the single user detection performance bound with only 0.5dB loss. The RC-JDD scheme has only 10% complexity of JDD scheme with only 0.5dB loss. Thus the proposed RC-JDD scheme can be a good candidate for 5G system.

Nonlinear function calculation is widely used in numerous science and technology fields. Stochastic computation is a novel high-efficiency value representation and calculation scheme, which is helpful to reduce hardware cost. However, the main challenges of stochastic computation based nonlinear function implementation lie on poor generalization, low accuracy and high latency. In this paper, we propose a multiple driving and multiple dimension finite state machine (MM-FSM) to realize major single variable nonlinear functions used in information and signal processing areas on common platforms with low complexity and latency. We provide corresponding synthesis method of the activation parameters and conditional parameters of MM-FSM. In order to improve the calculation accuracy, we further propose an adaptive scaling algorithm for MM-FSM. The most salient feature of MM-FSM is that we can configure different types of nonlinear functions with the same MM-FSM structure. Thus, MM-FSM can be used in a wide range of stochastic based applications. Compared with the traditional stochastic scheme and Coordinate Rotation Digital Computer (CORDIC) algorithm, simulation results show that the proposed MM-FSM nonlinear function generator has significantly lower complexity while guaranteeing the calculation accuracy.