With the rapid development of the Internet of Things (IoT), device and data security has attracted huge academic attention in recent years since conventional security methods are barely feasible in IoT circumstances. Traditional encryption methods require extensive computation complexity, which requires several hardware resources and power consumption. Meanwhile, due to the low power requirement, most IoT devices are lightweight with limited computing and storage capabilities. The dilemma leads to the need for a lightweight encryption method with decent data protection strength. Chaotic encryption can be applied in the IoT because of the characteristics of determinacy and strong randomness. However, its safety and hardware overhead are positively correlated with implementation precision. Therefore, this paper performs a quantitative analysis of the system under different precision conditions. Then, a hybrid chaotic encryption scheme with dynamic precision is proposed, which balances power consumption and security protection level. Finally, the proposed design is implemented by Verilog and synthesized using SMIC 65nm CMOS technology. The evaluation results proved that the proposed ASIC provides decent encryption strength under diverse precision, effectively overcoming the influence of limited precision with low hardware resources and power consumption.

Hybrid low-density parity-check (LDPC) decoding combines conventional Belief-Propagation (BP) algorithm with stochastic decoding to achieve high performance and low complexity simultaneously. However, lossy and inefficient stochastic-to-binary (S2B) conversion brings extra performance degradation and decoding latency. In this paper, a bit-serial stochastic updating based hybrid decoding (BSSU-HD) is proposed, which employs fully correlated stochastic (FCS) check nodes (CNs) and probability tracers assisted variable nodes (VNs) to accomplish accurate and efficient S2B conversion. Two strategies, including random source selection and tracing speed switching, are proposed to further improve performance and convergence. A BSSU LDPC decoder for IEEE 802.3an is designed in a 65-nm CMOS process, which occupies 4.6 mm $^2$ silicon area and achieves a throughput of 200.8 Gb/s at $E_b/N_0 = 4.4$ dB with 500 MHz clock frequency from a 1.2 V supply voltage. The power and energy efficiency are 2.933 W and 14.61 pJ/bit, respectively. To the best of our known, it achieves the best decoding performance, the highest throughput and hardware efficiency among state-of-the-art IEEE 802.3an LDPC decoders. We also verify that the BSSU-HD can achieve better performance for multi-rate 5th generation (5G) New Ratio (NR) LDPC codes than conventional algorithm, which greatly extends the application of the stochastic decoding.

Nonlinear functions are widely involved in modern digital signal processing systems, which are usually calculated by polynomial approximation, CORDIC algorithm, or look-up tables. Due to the quite complex logic computing architectures, these methods suffer from high switching activity of logic elements, resulting in tremendous dynamic power consumption. Reducing the switching activity is believed an efficient way to save dynamic power. In this brief, we first analyzed and proved the low switching activity feature of the conventional unary number representation. Afterward, a novel multi-hot unary number representation method and the corresponding logic computing architecture with low switching activity are proposed for nonlinear function, which significantly reduces switching activity and power consumption. Moreover, the proposed nonlinear function logic computing architecture is extended to single input multiple output nonlinear function calculation, which shares the multi-hot encoder to further reduce the hardware cost. According to the post-synthesis power evaluation using PrimePower tools, the proposed architecture achieves significant switching activity and dynamic power reduction compared to conventional computing architectures.

Digital filter is an important fundamental component in digital signal processing (DSP) systems. Among the digital filters, the finite impulse response (FIR) filter is one of the most commonly used schemes. As a low-complexity hardware implementation technique, stochastic computing has been applied to overcome the huge hardware cost problem of high-order FIR filters. However, the stochastic FIR filter (SFIR) scheme suffers from long processing latency and accuracy degradation. In this paper, the bit stream representation noise is theoretically analyzed, and an adaptive scaling algorithm (ASA) is proposed to improve the accuracy of SFIR with the same bit stream length. Furthermore, a novel antithetic variables method is proposed to further improve the accuracy. According to the simulation results on a 64-tap FIR filter, the ASA and AV methods gain 17 dB and 6 dB on the signal-to-noise ratio (SNR), respectively. The hardware implementation results are also presented in this paper, which illustrates that the proposed ASA-AV-SFIR filter increases 4.6 times hardware efficiency with respect to the existing SFIR schemes.

Massive multiple-input multiple-output (MIMO) is a core technology in the fifth-generation new radio (5G-NR) and the future mobile communication systems. However, MIMO detection poses a significant challenge due to its high computational complexity. This article proposes a low-complexity and fast-converging MIMO detector for multisubcarrier systems, termed matrix propagation (MP) noise-free initialization with momentum (MPNF-IM). Built on a training-assisted, stochastic gradient descent (SGD)-based iterative model, MPNF-IM accelerates convergence by reducing gradient variance, smoothing convergence behavior, and exploiting cross-subcarrier MP. Simulation results demonstrate that the proposed strategy achieves comparable bit error rate (BER) performance to existing detectors that integrate multilayer perceptron (MLP) and SGD, with deviations of up to 0.5 dB at $10^{-3}$ BER. Additionally, a hardware-efficient architecture is proposed, combining the interleaved pipeline and the mixed-precision deployment, along with a hybrid pipeline-iterative scheduling, to significantly improve hardware efficiency. Synthesized under the semiconductor manufacturing international corporation (SMIC) 65-nm CMOS technology, the design achieves a normalized area efficiency of 3.38 Gbps/MGE in a $32\times 4$ system, representing a $1.33\times $ improvement over the existing solutions with 53% lower detection latency. For a larger $128\times 8$ system, the proposed design maintains competitive area efficiency of 0.674 Gbps/MGE, achieving $1.13\times $ – $3.22\times $ improvement over prior designs, while simultaneously delivering superior energy efficiency.