The protection of processor-based systems to mitigate the harmful effect of transient faults (soft errors) is gaining importance as technology shrinks. At the same time, for large segments of embedded markets, parameters like cost and performance continue to be as important as reliability. This paper presents a compiler-based methodology for facilitating the design of fault-tolerant embedded systems. The methodology is supported by an infrastructure that permits to easily combine hardware/software soft errors mitigation techniques in order to best satisfy both usual design constraints and dependability requirements. It is based on a generic microprocessor architecture that facilitates the implementation of software-based techniques, providing a uniform isolated-from-target hardening core that allows the automatic generation of protected source code (hardened code). Two case studies are presented. In the first one, several software-based mitigation techniques are implemented and evaluated showing the flexibility of the infrastructure. In the second one, a customized fault tolerant embedded system is designed by combining selective protection on both hardware and software. Several trade-offs among performance, code size, reliability, and hardware costs have been explored. Results show the applicability of the approach. Among the developed software-based mitigation techniques, a novel selective version of the well known SWIFT-R is presented.

Large digital integrated circuits designed to solve space applications, have to be designed following standards that recommend to include hardening techniques against Single Event Phenomena caused by harsh radiation environments. It is specifically important in the case of modern deep-submicron technologies. Single Event Effects are phenomena related to the effects of radiation when ionizing particles hit the surface of semiconductors in certain critical areas, where the consequences are mainly data corruption or unexpected behavior with no permanent damage. Fault injection studies are a valuable methodology to evaluate the robustness of the circuit mainly in the early stages of the design. This paper introduces the second generation of the emulation-based fault injection platform FTUNSHADES supported by the European Space Agency, where new features have been included to fulfill with the demands of a growing community of users.

VLSI circuits for space application must be protected by the insertion of massive redundancy. However, this increases silicon area and the production costs, therefore designers can often consider leaving some large, noncritical subcircuits unprotected. This paper presents how FT-UNSHADES, a nonintrusive tool for fault injection on emulated hardware, helps designers to select the proper level of protection in every subcircuit. Using FT-UNSHADES, a test procedure is proposed that provides: 1) information about the quality of the test vectors, 2) a proper estimation of the number of injected faults required to get confidence about the results of a fault injection campaign, and 3) information about the criticality of individual subcircuits by selective fault injection campaigns. In addition, FT-UNSHADES allows the insertion of multi-bit flips. This test procedure has been applied to three different, protected and unprotected, versions of the well-known Leon2 processor, and the results are discussed here.

There is an increasing concern about the mitigation of radiation effects in embedded systems. This fact is demanding new flexible design methodologies and tools that allow dealing with design constraints and dependability requirements at the same time. This paper presents a novel proposal to design radiation-tolerant embedded systems combining hardware and software mitigation techniques. A hardening infrastructure, which facilitates the design space exploration and the trade-offs analyses, has been developed to support this fault tolerance co-design approach. The advantages of our proposal are illustrated by means of a case study.

Today, many companies are facing the problem of component obsolescence in embedded systems. The incredibly fast growth rate of semiconductor companies is reducing dramatically the time components are available on the market. Twenty years ago, components remained on the market for 5 to 10 years; nowadays, they disappear from the market in less than two years. Developers of safety- or mission-critical systems are particularly sensitive to the obsolescence problem as their systems are expected to remain operative for very long periods (e.g., 30 years or more), and maintaining them fully operative is becoming difficult as the needed components may no longer be available. A possible solution for this problem may be the implementation of the needed components using FPGAs. The purpose of this paper is to provide an overview of the different possibilities designers have to face when developing such dependability-oriented solution. Also, a design flow is presented, describing its applicability to the implementation of processor cores, to be employed as a replacement of obsolete parts in safety- or mission-critical applications. Results show that there is a strong dependence of the reliability of the design with the specific application. The scrubbing process can also be optimized using the related technique.

In critical digital designs such as aerospace or safety equipment, radiation-induced upset events (single-event effects or SEEs) can produce adverse effects, and therefore, the ability to compare the sensitivity of various proposed solutions is desirable. As custom-hardened microprocessor solutions can be very costly, the reliability of various commercial off-the-shelf (COTS) processors can be evaluated to see if there is a commercially available microprocessor or microprocessor-type intellectual property (IP) with adequate robustness for the specific application. Most existing approaches for the measurement of this robustness of the microprocessor involve diverting the program flow and timing to introduce the bit flips via interrupts and embedded handlers added to the application program. In this paper, a tool based on an emulation platform using Xilinx field programmable gate arrays (FPGAs) is described, which provides an environment and methodology for the evaluation of the sensitivity of microprocessor architectures, using dynamic runtime fault injection. A case study is presented, where the robustness of MicroBlaze and Leon3 microprocessors executing a simple signal processing task written in C language is evaluated and compared. A hardened version of the program, where the key variables are protected, has also been tested, and its contributions to system robustness have also been evaluated. In addition, this paper presents a further improvement in the developed tool that allows not only the measurement of microprocessor robustness but, in addition, the study and classification of single-event upset (SEU) effects and the exact measurement of the recovery time (the time that the microprocessor takes to self repair and recover the fault-free state). The measurement of this recovery time is important for real-time critical applications, where criticality depends on both data correctness and timing. To demonstrate the proposed improvements, a new software program that implements two different software hardening techniques (one for Data and another for Control Flow) has been made, and a study of the recovery times in some significant fault-injection cases has been performed over the Leon3 processor.