As chip technologies scale down in size, multiple adjacent logic nodes are often affected by a single high-energy ion strike. The so-called pulse quenching effect, induced by single-event charge sharing collection, has a significant effect on single-event transients (SETs). In this paper, the effect of pulse quenching on SETs is quantitatively characterized in 65-nm twin-well and triple-well CMOS technologies. Two groups of heavy ion experiments on two inverter chains were performed for the characterizations, and the effect of pulse quenching on SETs was quantitatively analyzed in detail.
25 February 2012 in Science China Technological Sciences
Analog single-event transient (ASET) and total ionizing dose (TID) characterization of a radiation-hardened bandgap voltage reference (BGR) is investigated in a 28-nm commercial bulk CMOS technology. Different radiation hardened by design (RHBD) techniques are used for ASET mitigation in the circuit and layout, and the circuit is optimized to ensure the BGR can still work correctly even using fast nMOS and slow pMOS for TID mitigation. Heavy-ion (linear energy transfer (LET) = 76.3 MeV $\cdot $ cm 2 /mg) experiments show the maximum amplitude of positive (negative) ASET is just 30 mV (90 mV), and Co 60 gamma-ray experiments show the maximum output voltage reduction is just 37 mV after 1.2 Mrad(Si) irradiation, and the final output voltage reduction is just 11 mV after 48 h of annealing. All of the experiments indicate that ASET is significantly mitigated by the RHBD techniques, and the BGR has naturally good TID response due to the design margin. The investigation also indicates that the proposed BGR is a good substitute for space application due to the excellent ASET and TID tolerance capability.
1 September 2013 in International Journal of Systems Science
In this article, by using the fractional order PIλ controller, we propose a simple and effective method to compute the robust stability region for the fractional order linear time-invariant plant with interval type uncertainties in both fractional orders and relevant coefficients. The presented method is based on decomposing the fractional order interval plant into several vertex plants using the lower and upper bounds of the fractional orders and relevant coefficients and then constructing the characteristic quasi-polynomial of each vertex plant, in which the value set of vertex characteristic quasi-polynomial in the complex plane is a polygon. The D-decomposition method is used to characterise the stability boundaries of each vertex characteristic quasi-polynomial in the space of controller parameters, which can obtain the stability region by varying λ orders in the range (0, 2). These regions of each vertex plant are computed by using three stability boundaries: real root boundary (RRB), complex root boundary (CRB) and infinite root boundary (IRB). The method gives the explicit formulae corresponding to these boundaries in terms of fractional order PIλ controller parameters. Thus, the robust stability region for fractional order interval plant can be obtained by intersecting stability region of each vertex plant. The robustness of stability region is tested by the value set approach and zero exclusion principle. Our presented technique does not require sweeping over the parameters and also does not need linear programming to solve a set of inequalities. It also offers several advantages over existing results obtained in this direction. The method in this article is useful for analysing and designing the fractional order PIλ controller for the fractional order interval plant. An example is given to illustrate this method.
Total ionizing dose (TID) radiation response of the custom bandgap voltage reference (BGR) fabricated with 65 nm, 40 nm and 28 nm commercial bulk CMOS technologies is investigated. TID response is assessed employing Co-60 gamma ray source. The measurements indicate that the voltage reference is reduced by 5.67% in 28 nm, 0.56% in 40 nm and increased by 1.28% in 65 nm devices under irradiation up to 1.2 Mrad(Si) TID. After 48 hours of annealing, the voltage reference changes are just -1.84% in 28 nm, 0.14% in 40 nm and 1.14% in 65 nm. The obtained results demonstrate that the custom BGR has naturally superior TID response due to the circuit design margins.