In this work, we report on back-end-of-line (BEOL)-compatible InGaZnO indium gallium zinc oxide (IGZO) thin film transistors (TFTs) with extreme scaled device dimension including channel thickness ( $\textit{T}_{\text{ch}}\text{)}$ down to 1.5 nm and channel length ( $\textit{L}_{\text{ch}}\text{)}$ down to 60 nm. These IGZO channels with a high In atomic ratio of 92% were derived by atomic-layer-deposition (ALD), where the IGZO thickness could be precisely controlled by ALD cycles. These TFTs were subjected to a mild O $_{\text{2}}$ annealing at 250 $^{\circ}$ C, the effect of which is also systematically investigated. It is found that both $\textit{T}_{\text{ch}}$ and O $_{\text{2}}$ annealing have significant effects on TFT performance. By using optimized O $_{\text{2}}$ annealing conditions, the ALD IGZO TFTs with scaled $\textit{T}_{\text{ch}}$ of 1.5 nm and $\textit{L}_{\text{ch}}$ of 60 nm exhibit desirable electrical performance including a high ON/OFF ratio ( $\textit{I}_{\biosc{on}}$ / $\textit{I}_{\biosc{off}}\text{)}$ $\sim$ 10 $^{\text{11}}$ , a decent high Ion of 354 $\mu$ A/ $\mu$ m under $\textit{V}_{\text{DS}}$ of 1.2 V, a steep subthreshold swing (SS) of 68 mV/dec, a small drain-induced-barrier-lowering (DIBL) of 30 mV/V, and a normal-off operation, which is comparable to the state-of-art sputtered IGZO TFTs. Furthermore, the optimized TFTs also exhibit significantly resolved threshold voltage ( $\textit{V}_{\text{T}}\text{)}$ roll-off and a remarkably high degree of stability to the positive gate bias stress (PBS). A trap model with its possible microscopic origin is proposed, which explains well the dependence of electrical performance on both $\textit{T}_{\text{ch}}$ and O $_{\text{2}}$ annealing, thus providing a new insight into the reliability of IGZO TFTs.

In this work, we report atomic-layer-deposited (ALD) based all-oxide transistors toward vertically stacked high-density logic and memory for 3-D integration. This structure utilizes thick degenerated ALD In $_{\text{2}}$ O $_{\text{3}}$ as the conducting gate, and ALD In $_{\text{2}}$ O $_{\text{3}}$ thin film itself serves as source/drain contacts to the ALD In $_{\text{2}}$ O $_{\text{3}}$ channel without metal contacts and gate formation. The all-oxide field-effect transistors (AOFETs) not only survived under high-temperature annealing over 400 $^{\circ}$ C but also gained a boosted ON-/OFF-ratio over 10 $^{\text{7}}$ with subthreshold swing (SS) close to 60 mV/dec at room temperature. AOFETs present high uniformity and very robust reliability with a threshold voltage instability ( ${\boldsymbol}{\Delta} \textit{V}_{\text{TH}}\text{)}$ of $-$ 5 and $-$ 50 mV under positive bias stress (PBS) and negative bias stress (NBS) tests for 10 $^{\text{4}}$ s. The vertical AOFETs (V-AOFETs) demonstrate good gate modulation from sidewall In $_{\text{2}}$ O $_{\text{3}}$ with thickness as well as gate length ( $\textit{T}_{\text{IO,\textit{g}}}\text{)}$ of 10 nm, achieving ON-/OFF-ratio over 10 $^{\text{5}}$ and maximum current ( $\textit{I}_{\text{max}}\text{)}$ over 160 ${\boldsymbol}{\mu} $ A/ ${\boldsymbol}{\mu} $ m. Vertical all-oxide ferroelectric FETs (V-AO-FeFETs) show a memory window (MW) of 1.85 V, with endurance and retention extended to 10 $^{\text{12}}$ cycles and ten years at room temperature, respectively. These findings illustrate that the vertical-channel all-oxide devices based on ALD oxide semiconductors (OS) are promising candidates for future high-density logic and memory applications in 3-D integration.

Cu-to-Cu thermal compression bonding (TCB) has emerged as a promising solution for ultrafine pitch packaging in 3D integrated circuit technologies. Despite the progress made by conventional Cu-to-Cu TCB methods in achieving good mechanical strength of the Cu bonds, the bonding processes generally require high temperature and high pressure, which may degrade the performance and reliability of the device. Therefore, it is imperative to investigate the processing parameters to understand the bonding mechanism and achieve effective TCB at a low temperature and low pressure. Here, we developed an in situ TCB technique inside a scanning electron microscope. The in situ TCB method enables a real-time observation of bonding development, which provides critical insights into how the texture and microstructure of Cu bumps may influence the creep and surface diffusion during the bonding process. This work features a strategy to advance our understanding of the bonding mechanisms and provides insight into tailoring the microstructure of Cu for bonding at a low temperature and low pressure.

In this work, we systematically investigated the effects of gallium (Ga) incorporation on electron transport and bias stability in ultrascaled InGaO transistors with channel thickness (T_ch) of 3 nm and scaled channel length (L_ch) down to 60 nm. It is found that Ga atoms act as carrier suppressors in the In₂O₃ host, resulting in a positively shifted threshold voltage (V_th) and a concurrent reduction in field-effect mobility (μ_FE) as Ga concentration increases. Notably, the shift in V_th (ΔV_th) of InGaO transistors during positive gate bias stability (PBS) tests transitions from negative to positive with increasing Ga concentration. This behavior is explained by the trap neutrality level (TNL) model, which defines the energy level at which positively charged donor-like traps are balanced by negatively charged acceptor-like traps. The relative position of the Fermi level (E_F) in In_XGaO with respect to the TNL determines whether donor-like or acceptor-like traps dominate the charge trapping behavior. Ga incorporation modifies the electronic nature of interface traps by reducing donor-like oxygen vacancies and introducing acceptor-like excessive oxygen states due to its strong oxygen-gettering effect. This study elucidates the crucial role of Ga in electron transport and bias stability in ultrascaled amorphous InGaO transistors, providing valuable guidance for designing In₂O₃-based transistors with high ON-state and stability performance while also shedding light on the interfacial trap dynamics in the ultrascaled regime.