This paper presents a time-domain analysis of an N-bit pulse-width-modulated digital-to-analog converter (PWM DAC) employing a first-order passive resistor-capacitor (RC) filter. Exact analytical expressions are derived for the output settling time in both rising and decreasing digital-code transition modes. The worst-case condition is identified, and the settling-time criterion is expressed as a function of the DAC resolution N, tolerance ε, and normalized filter parameter k = T/RC. The derived criterion is compared with a commonly used first-order RC settling approximation. For N = 8 and ε = 1/4, the proposed worst-case criterion gives a discrete settling interval of 823 PWM periods, whereas the literature-based estimate gives 355 periods. The analytical results are confirmed by numerical evaluation and LTspice transient simulations and are further supported by experimental measurements obtained using a microcontroller-based PWM generator and a passive RC filter. The results confirm the duty-cycle dependence of the steady-state ripple and demonstrate that the proposed criterion provides a conservative design rule for selecting PWM DAC parameters while balancing accuracy, ripple, and settling speed.