This paper presents a time-domain analysis of an N-bit pulse-width-modulated digital-to-analog converter (PWM DAC) employing a first-order passive resistor-capacitor (RC) filter. Exact analytical expressions are derived for the output settling time in both rising and decreasing digital-code transition modes. The worst-case condition is identified, and the settling-time criterion is expressed as a function of the DAC resolution N, tolerance ε, and normalized filter parameter k = T/RC. The derived criterion is compared with a commonly used first-order RC settling approximation. For N = 8 and ε = 1/4, the proposed worst-case criterion gives a discrete settling interval of 823 PWM periods, whereas the literature-based estimate gives 355 periods. The analytical results are confirmed by numerical evaluation and LTspice transient simulations and are further supported by experimental measurements obtained using a microcontroller-based PWM generator and a passive RC filter. The results confirm the duty-cycle dependence of the steady-state ripple and demonstrate that the proposed criterion provides a conservative design rule for selecting PWM DAC parameters while balancing accuracy, ripple, and settling speed.

A pulse-width-modulated (PWM) output followed by a first-order resistor–capacitor (RC) filter provides a low-cost approach to digital-to-analog conversion. This paper develops a resolution expansion of a reference expression for the continuous rising-transition settling count in the parameter δ = 2^−N, retaining the tolerance ε exactly. Here N denotes the resolution, and ε is expressed as a fraction of one least significant bit. The coefficients contain half-integer powers of ε and therefore have a Puiseux-type form. The first-order expression removes the exponential quotient of the reference expression and makes the dependence on N and ε explicit. Two higher-order truncations are also derived. For 1/8 ≤ ε < 1/2, the first and second truncations are proved never to underestimate the reference count. Both coincide with it at ε = 1/8. Over 1122 combinations with N = 4–20 and ε = 0.125–0.45, the maximum errors relative to the reference count are 0.21, 0.050, and 0.0025 PWM periods, with rounded-count agreement of 89.66%, 99.82%, and 100%, respectively. At every tested combination, the reference expression and the exact first-order model give the same rounded rising-transition count, and adding one period to each rounded truncated count covers the exact worst-case count over both transition directions. Both results are numerical and are established only for the tested grid.