As a heterogeneous integration technology, the chiplet-based design technology integrates multiple heterogeneous dies of diverse functional circuit blocks into a single chip by using advanced packaging technology, which is a promising way to tackle the failure of Moore’s law and Dennard scaling. Currently, as process nodes move forward, dramatically rising cost, design cycle, and complexity are driving industry to focus on the chiplets. Chiplets allows IC designers to merge dies fabricated at different process nodes and reuse them in different projects, which helps to reduce the cost during design and improve yield. In this review, we look back at the industry’s efforts over the past decade and summary the concepts and techniques associated with chiplets. In the end, a discussion and conclusion will be given to forecast the future of chiplets.

Polaronic configurations that were introduced by oxygen vacancy in rutile TiO₂ crystal have been studied by the DFT + U method. It is found that the building block of TiO₆ will expand when extra electron is trapped in the central Ti atom as polaron. With manually adjusting the initial geometry of oxygen vacancy structure, a variety of polaronic configurations are obtained after variable-cell relaxation. By calculating different sizes of supercell model, it is found that the most stable configuration can be influenced by the density of oxygen vacancy. With increasing interaction between vacancies, the most stable polaronic configuration change from small polaronic configuration to mixed configuration.

As of today, the semiconductor industry has been looking for possible alternative materials of silicon, since the physical limitation of silicon-based devices, i.e., planar CMOS devices for most of the scenarios, is approaching soon. Among all the novel materials arising from the horizon, graphene is considered to be a very promising alternative for its unique electrical properties. Although all kinds of prospective electrical properties it has(e.g., high mobility), there are barriers for Graphene-based Field Effect Transistors (G-FETs) to overcome, in order to find its way to the substitution of Silicon Metal Oxide Semiconducting Field Effect Transistors (Si-MOSFETs). One of the most important engineering barriers to be overwhelmed is the parasitic parameters, among which the parasitic resistance is considered to be one of the most critical roadblock. Contact resistance in G-FETs is relatively high compared to that of conventional Si-MOSFETs. In this paper, we present an experimental demonstration of a new method to reduce the contact resistance in back gate G-FETs. In the proposed device structure, the source/drain regions are fabricated using multilayer graphene (MLG), thus the top and edge contacts are formed between the MLG and metal electrodes, while the conducting channel is still formed by using single-layer graphene (SLG). Due to the high conductivity of MLG and relative low conductivity of SLG, the contact resistance is reduced while the controllability of channel conductivity is preserved.