Based on an analytical surface potential and a simple mathematical approximation for the source depletion width, a physics-based capacitance model with closed form for silicon double-gate tunnel field-effect transistors (TFETs) is developed. Good agreements between the proposed model and the numerical simulations have been achieved, which reveal that the tunneling carriers from source have negligible contribution to the channel charges and the gate capacitance can be almost acted as the gate-drain capacitance, which is quite different from that of MOSFETs. This model without involving any iterative process is more SPICE friendly for circuit simulations compared with the table-lookup approach and would be helpful for developing the transient performance of TFET-based circuits.

With the development of high-voltage and high-frequency switching circuits, GaN high-electron-mobility transistor (HEMT) devices with high bandwidth, high electron mobility, and high breakdown voltage have become an important research topic in this field. It has been found that GaN HEMT devices have a drift in threshold voltage under the conditions of temperature and gate stress changes. Under high-temperature conditions, the difference in gate contact also causes the threshold voltage to shift. The variation in the threshold voltage affects the stability of the device as well as the overall circuit performance. Therefore, in this paper, a review of previous work is presented. Temperature variation, gate stress variation, and gate contact variation are investigated to analyze the physical mechanisms that generate the threshold voltage (V_TH) drift phenomenon in GaN HEMT devices. Finally, improvement methods suitable for GaN HEMT devices under high-temperature and high-voltage conditions are summarized.

The damage mechanism of proton irradiation in InP/InGaAs heterostructures was studied. The deep level traps were investigated in detail by deep level transient spectroscopy (DLTS), capacitance–voltage (C–V) measurements and SRIM (the stopping and range of ions in matter, Monte Carlo code) simulation for non-irradiated and 3 MeV proton-irradiated samples at a fluence of 5 × 10¹² p/cm². Compared with non-irradiated samples, a new electron trap at E_C-0.37 eV was measured by DLTS in post-irradiated samples and was found to be closer to the center of the forbidden band. The trap concentration in bulk, the interface trap charge density and the electron capture cross-section were 4 × 10¹⁵ cm⁻³, 1.8 × 10¹² cm⁻², and 9.61 × 10⁻¹⁵ cm², respectively. The deep level trap, acting as a recombination center, resulted in a large recombination current at a lower forward bias and made the forward current increase in InP/InGaAs heterostructures for post-irradiated samples. When the deep level trap parameters were added into the technology computer-aided design (TCAD) simulation tool, the simulation results matched the current–voltage measurements data well, which verifies the validity of the damage mechanism of proton irradiation.

The nanowire gate-all-around structure with the ultimate channel electrostatic integrity exhibits the best immunity to short channel effects and improved scaling capability compared with other multigate structures. In this article, both the tunneling current and capacitance models are developed simultaneously for nanowire tunneling field-effect transistors (FETs). Based on the same surface potential model, the developed current model and capacitance model share the common parameters and therefore can be easily integrated as a complete model for circuit-level simulations. Moreover, there is no iterative process involved during the model derivation indicating the models would be efficient for circuit simulations. The proposed models are also implemented into a circuit simulator with SPICE net-list to simulate the inverter, NAND, and NOR gates. Correct circuit behaviors obtained validate the model compatibility with the SPICE platform and usefulness for the further investigation of nanowire-based tunnel FET (TFET) circuits.

In this paper, a universal analytical current model for a double-gate Si-based tunnel field-effect transistor (TFET) is presented considering the effects of charges in source depletion region and channel. An accurate surface potential model is developed first by solving the pseudo-2-D Poisson equations in the depletion regions, and then is used to calculate the drain tunneling current. The modeling results match well with that obtained from the Technology computer-aided design simulations under various biasing conditions, which indicate that the analytical current model would be very helpful for the further TFET-based circuits design. Furthermore, the influence of the source depletion is also studied, and the presented model with considering the source depletion region and the channel inversion charges is proved to be much more accurate than that ignoring the source depletion.

The practical use of tunnel field-effect transistors is retarded by the low on-state current. In this paper, the energy-band engineering of InAs/Si heterojunction and novel device structure of source-pocket concept are combined in a single tunnel field-effect transistor to extensively boost the device performance. The proposed device shows improved tunnel on-state current and subthreshold swing. In addition, analytical potential model for the proposed device is developed and tunneling current is also calculated. Good agreement of the modeled results with numerical simulations verifies the validation of our model. With significantly reduced simulation time while acceptable accuracy, the model would be helpful for the further investigation of TFET-based circuit simulations.