This article presents a third-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC), which exploits a hybrid error control topology to increase the order of the noise-transfer function (NTF). This scheme is a hybrid of two NS stages, namely, a cascaded integrator feed-forward (CIFF) and an error feedback (EF). This EF-CIFF structure contributes a more effective NS capability and enhances the robustness of the high-order NTF. An improved dither-based digital calibration is developed to mitigate the harmonic distortion caused by the capacitor mismatch. Due to the usage of an averaging filter, this calibration greatly reduces the interference of quantization noise on mismatch extraction while only needing a minimum modification in a standard SAR Topology. Hence, our scheme is simple and inherently robust to the process, voltage, and temperature variation. Based on an 8-bit SAR, our prototype is fabricated in a 130-nm CMOS process. It consumes a 96- $\mu \text{W}$ power when operating at a 2-MS/s sampling frequency with a 1.2-V supply. The proposed NS-SAR yields a peak Schreier figure of merit of 170.7 dB with a signal-to-noise-and-distortion ratio (SNDR) of 79.57 dB at an oversampling ratio of 8.

This paper proposes a high area-efficiency 14-bit column-parallel successive approximation register (SAR) analog-to-digital converter (ADC) for array sensors. A novel hybrid capacitor digital-to-analog converter (CDAC) based on the charge transfer is utilized to increase the area efficiency. It consists of a 9-bit split CDAC and a 5-bit serial CDAC. A foreground digital calibration is employed to compensate for the linearity error caused by the capacitor mismatch and bridge parasitic capacitor. The prototype was designed and fabricated in a 130-nm CMOS technology. Sampling at 200KS/s, the total power consumption is 57 μW. With the digital calibration, the proposed ADC achieves the Spurious Free Dynamic Range (SFDR) of 89.14 dB and the Differential Nonlinearity (DNL) of 0.87/-0.99 LSB. The single ADC occupies an active area of 15 × 1450 μm ² and the area efficiency is only 6.77 μm ² /code.

This article presents a 12-bit column-parallel two-step single-slope analog-to-digital converter (SS ADC). With the merging of analog memory capacitor and input sampling capacitor, the proposed two-step SS ADC realizes simultaneously residue storage and zero-cross detection. The fixed decision point guarantees a static comparator offset. A constant input common-mode level resistor ramp generator, which exploits a current-mode R-2R digital-to-analog converter (DAC) and a variable feedback R-string DAC, is developed to enhance ADC linearity limited by finite common-mode rejection ratio (CMRR) of the operational amplifier. Using a bottom-up foreground self-calibration, harmonic distortion caused by both parasitic capacitor and resistor mismatch is mitigated. This prototype is fabricated using a 130-nm CMOS process. The proposed two-step SS ADC consumes 62- $\mu \text{W}$ power when operating at a 100-KS/s sampling frequency and yields a peak spurious-free dynamic range (SFDR) of 76.47 dB with a signal-to-noise-and-distortion ratio (SNDR) of 60.78 dB. The measured differential nonlinearity (DNL) and the integral nonlinearity (INL) are 0.83/−1 and 4.78/−3.31 LSB, respectively.

This paper proposes a novel 12-bit column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for high-speed CMOS image sensors. Cooperating with the output offset storage (OOS) technique, a new correlated double sampling (CDS) is adopted to reduce the non-uniformity in column-level ADCs. In the proposed structure, the decision point of the comparator is independent of the input signal. The variation of the comparator offset caused by the input level is eliminated. Through a foreground calibration, the non-idealities from the ramp generator and the column ADC are both corrected. Design and simulation in a 130nm CMOS process, the proposed ADC achieves the differential nonlinearity (DNL) of +0.76/-0.8 LSB and the integral nonlinearity (INL) of +1.06/-0.84 LSB at a sampling frequency of 100 KS/s with the calibration. The effective number of bits (ENOB) is also improved from 4.66 bits to 11.25 bits. The single ADC occupies an active area of 7.5×775 μm2 and the power consumption is 72 μW.

This paper presents a subthreshold-leakage-current-based fully CMOS temperature-to-digital converter with high accuracy and supply rejection. The subthreshold current ratio is constructed by different channel lengths of the same MOSFET type, providing high accuracy and less corner dependence. In addition, the supply sensitivity is enhanced by the proposed subthreshold-leakage-current-based sensing element (SE) and the frequency ratio of two identical currents to frequency converters (CFCs). The prototype was implemented in a 180nm CMOS process. It achieves an inaccuracy of $\pm$ 0.8 $^{\circ}$ C (3 $\sigma )$ from 0 $^{\circ}$ C to 100 $^{\circ}$ C after two-point calibration with a resolution of 120mK. Over a wide supply range from 0.8V to 1.6V, the temperature sensor shows a supply sensitivity of 0.9 $^{\circ}$ /V at 30 $^{\circ}$ C. Over the temperature range of 0-100 $^{\circ}$ C, the power supply sensitivity is smaller than 3.4 $^{\circ}$ C/V. Operating at 1V, the sensor has a power consumption of 20nW at 30 $^{\circ}$ C, leading to an FoM of 14.4 pJ $\cdot$ K $^{2}$ .