A VCO-based(Voltage Controlled Oscillator) temperature sensor with multi-threshold MOSFET based sensing element is proposed. The proposed temperature sensor converts temperature variation into frequency and then into digital readings. In the proposed temperature sensor, the ratio of two reference currents, generated by P-MOSFETs operated in sub-threshold region and with different channel doping concentration, is used to sense the variation of temperature and achieves a 3σ inaccuracy of ±0.06°C after first-order poly-fit with systematic nonlinearity removal. The ratio of currents is then transformed into difference of the output frequencies of two identical CMOS-thyristor based VCOs, both of which are optimized to alleviate the impact of charge sharing and charge injection on the precision of the temperature sensor. In this way, there is no need for generating an external reference clock. The prototype is fabricated in a 130nm CMOS process and achieves an inaccuracy of +0.44°C/-0.4°C. The proposed sensor achieves a resolution of 0.1°C and a resolution FoM of 0.12nJ·K². The prototype occupies an area of 0.07mm².

This article presents a third-order noise-shaping (NS) successive approximation register (SAR) analog-to-digital converter (ADC), which exploits a hybrid error control topology to increase the order of the noise-transfer function (NTF). This scheme is a hybrid of two NS stages, namely, a cascaded integrator feed-forward (CIFF) and an error feedback (EF). This EF-CIFF structure contributes a more effective NS capability and enhances the robustness of the high-order NTF. An improved dither-based digital calibration is developed to mitigate the harmonic distortion caused by the capacitor mismatch. Due to the usage of an averaging filter, this calibration greatly reduces the interference of quantization noise on mismatch extraction while only needing a minimum modification in a standard SAR Topology. Hence, our scheme is simple and inherently robust to the process, voltage, and temperature variation. Based on an 8-bit SAR, our prototype is fabricated in a 130-nm CMOS process. It consumes a 96- $\mu \text{W}$ power when operating at a 2-MS/s sampling frequency with a 1.2-V supply. The proposed NS-SAR yields a peak Schreier figure of merit of 170.7 dB with a signal-to-noise-and-distortion ratio (SNDR) of 79.57 dB at an oversampling ratio of 8.

This paper proposes a high area-efficiency 14-bit column-parallel successive approximation register (SAR) analog-to-digital converter (ADC) for array sensors. A novel hybrid capacitor digital-to-analog converter (CDAC) based on the charge transfer is utilized to increase the area efficiency. It consists of a 9-bit split CDAC and a 5-bit serial CDAC. A foreground digital calibration is employed to compensate for the linearity error caused by the capacitor mismatch and bridge parasitic capacitor. The prototype was designed and fabricated in a 130-nm CMOS technology. Sampling at 200KS/s, the total power consumption is 57 μW. With the digital calibration, the proposed ADC achieves the Spurious Free Dynamic Range (SFDR) of 89.14 dB and the Differential Nonlinearity (DNL) of 0.87/-0.99 LSB. The single ADC occupies an active area of 15 × 1450 μm ² and the area efficiency is only 6.77 μm ² /code.

A digital calibration scheme is proposed to minimize the timing mismatch in time-interleaved analog-to-digital converters (TIADCs). First, the scheme is to subtract the outputs from adjacent channel ADCs and to utilize the expectations of the absolute value of the subtracted results to represent the actual sampling time interval. The timing mismatch is recognized by comparing these expectations. The obtained information is fed back to adjust variable delay buffers, thus reducing the timing mismatch. The application of this scheme to a 12-bit 1.6 GS/s four-channel TIADC is demonstrated. Simulation results show that with an input signal whose bandwidth is limited to the Nyquist frequency, the proposed timing mismatch calibration scheme is effective and capable of reducing the mismatch to the minimum. Compared with traditional calibration schemes, the proposed scheme is more feasible to implement and consumes less power and chip area.

This article presents a 12-bit column-parallel two-step single-slope analog-to-digital converter (SS ADC). With the merging of analog memory capacitor and input sampling capacitor, the proposed two-step SS ADC realizes simultaneously residue storage and zero-cross detection. The fixed decision point guarantees a static comparator offset. A constant input common-mode level resistor ramp generator, which exploits a current-mode R-2R digital-to-analog converter (DAC) and a variable feedback R-string DAC, is developed to enhance ADC linearity limited by finite common-mode rejection ratio (CMRR) of the operational amplifier. Using a bottom-up foreground self-calibration, harmonic distortion caused by both parasitic capacitor and resistor mismatch is mitigated. This prototype is fabricated using a 130-nm CMOS process. The proposed two-step SS ADC consumes 62- $\mu \text{W}$ power when operating at a 100-KS/s sampling frequency and yields a peak spurious-free dynamic range (SFDR) of 76.47 dB with a signal-to-noise-and-distortion ratio (SNDR) of 60.78 dB. The measured differential nonlinearity (DNL) and the integral nonlinearity (INL) are 0.83/−1 and 4.78/−3.31 LSB, respectively.

This paper proposes a novel 12-bit column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for high-speed CMOS image sensors. Cooperating with the output offset storage (OOS) technique, a new correlated double sampling (CDS) is adopted to reduce the non-uniformity in column-level ADCs. In the proposed structure, the decision point of the comparator is independent of the input signal. The variation of the comparator offset caused by the input level is eliminated. Through a foreground calibration, the non-idealities from the ramp generator and the column ADC are both corrected. Design and simulation in a 130nm CMOS process, the proposed ADC achieves the differential nonlinearity (DNL) of +0.76/-0.8 LSB and the integral nonlinearity (INL) of +1.06/-0.84 LSB at a sampling frequency of 100 KS/s with the calibration. The effective number of bits (ENOB) is also improved from 4.66 bits to 11.25 bits. The single ADC occupies an active area of 7.5×775 μm2 and the power consumption is 72 μW.