Jin Xu

Dr. Jin Xu


Research Focus & Metrics

Academic Career Length

24Years (2003-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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8 June 2018 in IEEE Transactions on Power Electronics
Verified
Journal Article
Closed access
KWKeyou Wang
Keyou Wang
JXJin Xu
Jin Xu
LI GUO JIELI GUO JIE
LI GUO JIE
Nengling TaiNengling Tai
Nengling Tai
ATAnping Tong
Anping Tong
JHJunxian Hou
Junxian Hou
Power converters in the system-level real-time simulation are usually emulated by L/C-based associated discrete circuit (L/C-ADC). However, the L/C-ADC approaches may suffer from two issues: how to mitigate the unacceptable virtual power loss especially in high-frequency applications, and how to tune LC parameters setting which is affected by the external circuit. This paper proposes a novel generalized associated discrete circuit (G-ADC) model with parameterized history current sources. By utilizing the stability region of the feasible parameter space, the optimized G-ADC models with the best damping characteristic are developed for both two-level and three-level converters. The analytical results also guarantee that the parameters of the optimized G-ADC model are independent of the external circuit for most power grid applications. Furthermore, an FPGA-based real-time simulation platform is built to verify the feasibility of the proposed scheme. Extensive simulation and hardware-in-loop (HIL) experiment results demonstrate the effectiveness and superiority of best-damped models as well as the modeling flexibility corresponding to insensitivity to operating conditions and external system parameters.

19 August 2019 in IEEE Transactions on Power Delivery
Verified
Journal Article
Closed access
JXJin Xu
Jin Xu
KWKeyou Wang
Keyou Wang
PWPan Wu
Pan Wu
LI GUO JIELI GUO JIE
LI GUO JIE
The real-time simulation based on the field programmable gate array (FPGA) is receiving more and more attention. However, up to now, the simulation scale for the power electronic system is not so satisfactory due to the real-time requirement and the FPGA resource limitation. This paper proposes a sub-microsecond level real-time simulation method for microgrids. The power converters are modeled with fixed-admittance models and simulated with a compact electromagnetic transients program (EMTP) algorithm. In the meanwhile, the distribution lines/cables are modeled with π-circuit models and simulated with a distributed circuit solution method, called the latency insertion method (LIM). As a result, the distribution generation (DG) systems are decoupled with each other and can be simulated in parallel. The case study shows that the proposed simulation method consumes much fewer FPGA resources compared with the traditional one. Besides, the time step can be much smaller and doesn't need to increase with the simulation scale. With these advantages, the real-time simulation of a microgrid consisting of 3 three-phase converters, 3 boost circuits and 21 three-phase lines can be achieved on the Xilinx Kintex-7 410T FPGA with a minimum time-step of 380ns.

1 August 2021 in IEEE Journal of Emerging and Selected Topics in Power Electronics
Verified
Journal Article
Closed access
JXJin Xu
Jin Xu
KWKeyou Wang
Keyou Wang
PWPan Wu
Pan Wu
ZLZirun Li
Zirun Li
YLYadong Liu
Yadong Liu
WZWeijie Zheng
Weijie Zheng
The switching frequency of power electronic devices has become much higher than before, which brings great challenges to real-time simulators. The small time-step in high switching frequency simulations remarkably increases the difficulty to satisfy the real-time requirement. This paper realizes the accurate real-time simulation of a solid-state transformer (SST) with a switching frequency of 50kHz at the time-step of 250ns on an FPGA-based platform. The hybrid companion circuit modeling method and the compact-EMTP (Electro-Magnetic Transient Program) algorithm are proposed in this paper to make sure the simulation loop can complete in less than one microsecond. The hybrid companion circuit modeling method can avoid too many digits used in representing simulation variables. The compact-EMTP algorithm is designed by combining the sequential computation tasks of the traditional EMTP to fully utilize the parallelized hardware structure of the FPGA. Besides, a circuit partition method is adopted to further parallelize the circuit solution of the SST circuit. In these ways, the simulation loop of the SST can be completed in 38 clock cycles (about 237.5ns). The simulation results show that the real-time simulation waveforms are almost consistent with those of the offline simulation software. Besides, the hardware-in-the-loop (HIL) simulation can also be performed on this platform to test the control functions of the SST.

5 May 2021 in IEEE Transactions on Industrial Electronics
Verified
Journal Article
Closed access
ZLZirun Li
Zirun Li
JXJin Xu
Jin Xu
KWKeyou Wang
Keyou Wang
GLGuojie Li
Guojie Li
PWPan Wu
Pan Wu
The L / C -based fixed-admittance model ( L / C model) is usually used in the real-time simulation for power electronic converters. However, the L / C switch model suffers from the problems of virtual power loss and complicated optimal parameter settings. This article proposes a small-step synthesis real-time simulation method suitable for power electronic converters. By modeling the power electronic converter with a small (nanosecond) time-step and simulating with a normal (microsecond) time-step, the issue of virtual power loss of the L / C model caused by the transient process after the switching action is solved. The real-time simulation experiments with different type converters based on one set of simulation parameters are carried out on field-programmable gate array separately to verify the insensitivity to converter topologies. Furthermore, the real-time simulation results of the small-step synthesis method using the L / C model are compared with those of the traditional electromagnetic transient program (EMTP) method using the L / C model and the R on / R off model. The simulation results provide verification of the effectiveness of the small-step synthesis method as well as the insensitivity to carrier frequencies, and L / C model parameters.

27 November 2020 in Protection and Control of Modern Power Systems
Verified
Journal Article
Open access
PDF file
ZLZirun Li
Zirun Li
JXJin Xu
Jin Xu
KWKeyou Wang
Keyou Wang
PWPan Wu
Pan Wu
LI GUO JIELI GUO JIE
LI GUO JIE
The electric vehicle (EV) charging station is a critical part of the infrastructure for the wide adoption of EVs. Real-time simulation of an EV station plays an essential role in testing its operation under different operating modes. However, the large numbers of high-frequency power electronic switches contained in EV chargers pose great challenges for real-time simulation. This paper proposes a compact electromagnetic transient program (C-EMTP) algorithm for FPGA-based real-time simulation of an EV station with multiple high-frequency chargers. The C-EMTP algorithm transforms the traditional EMTP algorithm into two parallel sub-tasks only consisting of simple matrix operations, to fully utilize the high parallelism of FPGA. The simulation time step can be greatly reduced compared with that of the traditional EMTP algorithm, and so the simulation accuracy for high-frequency power electronics is improved. The EV chargers can be decoupled with each other and simulated in parallel. A CPU-FPGA-based real-time simulation platform is developed and the proposed simulation of the EV station is implemented. The control strategy is simulated in a CPU with 100 μs time-step, while the EV station circuit topology is simulated in a single FPGA with a 250 ns time-step. In the case studies, the EV station consists of a two-level rectifier and five dual-active bridge (DAB) EV chargers. It is tested under different scenarios, and the real-time simulation results are validated using PSCAD/EMTDC.

14 June 2022 in IEEE Transactions on Industrial Electronics
Verified
Journal Article
Closed access
ZLZirun Li
Zirun Li
JXJin Xu
Jin Xu
KWKeyou Wang
Keyou Wang
GLGuojie Li
Guojie Li
PWPan Wu
Pan Wu
LZLei Zhang
Lei Zhang
The cascaded H-bridge (CHB)-based solid-state transformer (SST) is a core interface device for power conversion in the distribution network. However, the complicated structures and higher switching frequencies bring significant challenges to real-time simulation and hardware-in-loop (HIL) testing. This article proposes a field-programmable gate array (FPGA)-based hierarchical parallel real-time simulation method for cascaded SST, which mainly includes highly parallel solving at the operation level, module level, and system level. A dual-port equivalent model of the cascaded SST is constructed based on the hierarchical parallel real-time simulation method. A cascaded SST containing 42 modules (630 components) can be simulated on a single FPGA with a minimum of 400 ns time-step. The information of the ports of the equivalent model and the information of the internal nodes of the cascaded SST can be obtained, which is the same as the simulation of detailed model. The real-time simulation of cascaded SST with input-series-output-parallel (ISOP) structure is carried out on a Xilinx Kintex-7 FPGA. The simulation results show that the real-time simulation waveforms are almost consistent with those in PSCAD/EMTDC software package.