During the last ten years, the miniaturization of nanoscale field-effect transistors (FETs) predicted by Moore's law has confronted an aggressive scaling down of the FET architecture (geometry and material) of nanoelectronics devices including phone mobile and computers. Built on thinner Fin body, FinFETs technologies are nonplanar devices based on scalable architecture suitable for the industry and nanomanufacturing methods. However, those emerging nanodevices suffer from thermal challenges related to self-heating effects and highest heat dissipation caused by thermal penetration. In this article, we report the nanoscale thermal transport in sub 7-nm FinFETs technology based on phonon hydrodynamic equation (PHE). Furthermore, we highlight feasible strategies to enhance the heat ability, which can improve the thermal stability of the nanodevice. This work presents a new physical picture of thermal performance optimizations in existing and future nanoelectronics devices.

A flexible framework is obtained for enhancing both the thermal and electrical performance of fin field-effect transistor (FinFET) technology. Investigation of the nanoscale heat conduction within a short-channel field-effect transistor can be regarded as an emerging challenge related to future-generation transistors. In this work, we report the electrothermal transport in a 10 nm silicon-on-insulator (SOI) FinFET based on the dual-phase-lag model and modified drift-diffusion motions. We found that electron mobility decreases along the channel due to carrier confinement under higher electric field. In addition, the surface detection temperature indicates that the self-heating process is localized between the source and drain region. As promising results, high-κ metal-oxide and lower thermal boundary resistance can optimize the nanoscale heat transport in the SOI FinFET device.