Nonvolatile (NV) memory is a key element for future high-performance and low-power microelectronics. Among the proposed NV memories, spintronics-based ones are particularly attractive for applications, owing to their low-voltage and high-speed operation capability in addition to their high-endurance feature. There are three types of spintronics devices with different writing schemes: spin-transfer torque (STT), spin-orbit torque (SOT), and electric field (E-field) effect on magnetic anisotropy. The NV memories using STT have been studied and developed most actively and are about to enter into the market by major semiconductor foundry companies. On the other hand, a development of the NV memories using other writing schemes are now underway. In this review article, first, the recent advancement of the spintronics device using STT and the NV memories using them are reviewed. Next, spintronics devices using the other two writing schemes (SOT and E-field) are briefly reviewed, including issues to be addressed for the NV memories application.

The development of new functional memories using emerging nonvolatile devices has been widely investigated. Spin-transfer torque magnetoresistive random access memory (STT-MRAM) has become new technology platform to overcome the issue in power consumption of logic for the application from IoT to AI; however, STT-MRAM has a tradeoff relationship between endurance, retention, and access time. This is because the MTJ device used in STT-MRAM is a two-terminal device, and excessive read current for high-speed readout can cause unexpected data writing, or so-called read disturbance. In order to meet the demand for the realization of high-speed nonvolatile memory, the development of new memories based on innovative circuit, device, and integration process is required. In this article, we demonstrate an SOT-MRAM, a nonvolatile memory using MTJ devices with spin-orbit-torque (SOT) switching that have a read-disturbance-free characteristic. The SOT-MRAM fabricated using a 55-nm CMOS process is implemented in a dual-port configuration utilizing a three-terminal structure of the device for realizing a wide bandwidth applicable to high-speed applications. In addition, a read-energy reduction technique called a self-termination scheme is also implemented. Through the measurement results of the fabricated prototype chip, we will demonstrate the proposed SOT-MRAM achieves 60-MHz write and 90-MHz read operations with 1.2-V supply voltage under a magnetic-field-free condition.

We fabricated a quadruple-interface perpendicular magnetic tunnel junction (MTJ) (Quad-MTJ) down to 33 nm using physical vapor-deposition, reactive ion etching, and damage-control integration process technologies that we developed under a 300-mm process. We demonstrated the greater scalability and higher writing speed of Quad-MTJ compared with double-interface perpendicular MTJ: 1) it has twice the thermal stability factor--1X nm Quad-MTJ can achieve 10 years retention--while maintaining a low resistance-area product and high tunnel magnetoresistance ratio; 2) smaller overdrive ratio of write voltage to obtain a sufficiently low write-error rate; 2) smaller pulsewidth dependence of the switching current; and 4) more than double the write efficiency at 10-ns write operation down to 33-nm MTJ. The effective suppression of the switching current increase for higher write speeds was explained by the spin-transfer-torque model using the Fokker-Planck equation. Our 33-nm Quad-MTJ also achieved excellent endurance (at least 10¹¹) owing to its higher write efficiency and low-damage integration-process technology. It is thus a promising method for low power, high speed, and reliable STT-MRAM with excellent scalability down to the 1X nm node.

We have proposed a novel quad-interface magnetic tunnel junction (MTJ) technology which brings forth an increase of both thermal stability factor Δ and switching efficiency defined as the ratio of Δ to intrinsic critical current IC0 (Δ /IC0) by a factor of 1.5-2 compared with the conventional double-interface MTJ technology. The free layer of the developed quad interface consists of bottom-MgO/FL1/middle-MgO/FL2/top-MgO stack structure. We successfully fabricated the quad-interface MTJ using a 300-mm process based on a novel low-damage integration process including physical vapor deposition (PVD), reactive ion etching (RIE), and so on. By developing the quad-interface MTJ, we have achieved about two times larger Δ and Δ /IC0 at the same time. Moreover, we have achieved about two times larger tunnel magnetoresistance (TMR) ratio at the same resistance area (RA) product by developing the FL1, bottom-MgO, and middle-MgO. The developed quad-interface MTJ technology considered as post-double-interface MTJ technology will become an essential technology for the scaling of the spin-transfer-torque magnetoresistive random access memory (STT-MRAM) beyond 20 nm.

We successfully developed 25-nm quad CoFeB/MgO-interfaces perpendicular magnetic tunnel junction (quad-MTJ) with enough thermal stability. To fabricate the quad-MTJ, a physical vapor deposition (PVD) process for depositing novel free layer and low resistance-area (RA) product MgO layer and low-damage fabrication processes were developed. The developed quad-MTJ technology and advanced process bring better tunnel magneto resistance (TMR) ratio and RA to quad-MTJ than those of double-interface MTJ (double-MTJ), even though quad-MTJ has an additional MgO layer. Scaling down the MTJ size to 25 nm, we demonstrated the advantages of quad-MTJ compared with double-MTJ as follows: 1) two times larger thermal stability factor (Δ), which results in over ten years retention; 2) superiority of large Δ in the measuring temperature range up to 200 °C; 3) ~1.5 times higher write efficiency; 4) lower write current at short write pulse regions at less than 100 ns; and e) excellent endurance of over 10 ¹¹ thanks to higher write efficiency, which results from the reduced voltage owing to low RA and the low damage integration process technology. As a result, the developed quad-MTJ technologies will open the way for the realization of high-density STT-MRAM with low power, high speed, high reliability, and excellent scalability down to 2× nm node.

A novel nonvolatile static random access memory cell is proposed that consists of four transistors and two spin-transfer-torque magnetic tunnel junctions (STT-MTJs). In the case of the NFET driver cell, the free layers of the magnetic tunnel junctions are connected to the transistors' sources and drains to make the cell read-disturb free. The static power is totally eliminated as the power line is shut down during data hold. The static noise margin of the cell is calculated based on the experimental data on MTJ switching that is enhanced from the resistive load SRAM cell due to the MTJ's switching operation. The cell size is estimated to become smaller than the 6-transistor SRAM cell when it is designed at 45 nm node and beyond owing to the MTJ's area shrink as well as the thinning of its tunnel dielectrics (MgO).