This paper presents a novel low-power register file based on adiabatic logic. The register file consists of a storage-cell array, address decoders, read/write control circuits, sense amplifiers, and read/write drivers. The storage-cell array is based on the conventional memory cell. All the circuits except the storage-cell array employ CPAL (complementary pass-transistor adiabatic logic) to recover the charge of large node capacitance on address decoders, bit-lines and word-lines in fully adiabatic manner. The minimization of energy consumption was investigated by choosing the optimal size of CPAL circuits for large load capacitance. The power consumption of the proposed adiabatic register file is significantly reduced because the energy transferred to the large capacitance buses is mostly recovered. The energy and functional simulations are performed using the net-list extracted from the layout. HSPICE simulation results indicate that the proposed register file attains energy savings of 65% to 85% as compared to the conventional CMOS implementation for clock rates ranging from 25 to 200 MHz.

Micro-electromechanical system (MEMS) magnetic sensors are widely used in the nanosatellites field. We proposed a novel high-precision miniaturized three-axis digital tunneling magnetic resistance-type (TMR) sensor. The design of the three-axis digital magnetic sensor includes a low-noise sensitive element and high-performance interface circuit. The TMR sensor element can achieve a background noise of 150 pT/Hz^1/2 by the vertical modulation film at a modulation frequency of 5 kHz. The interface circuit is mainly composed of an analog front-end current feedback instrumentation amplifier (CFIA) with chopper structure and a fully differential 4th-order Sigma-Delta (ΣΔ) analog to digital converter (ADC). The low-frequency 1/f noise of the TMR magnetic sensor are reduced by the input-stage and system-stage chopper. The dynamic element matching (DEM) is applied to average out the mismatch between the input and feedback transconductor so as to improve the gain accuracy and gain drift. The digital output is achieved by a switched-capacitor ΣΔ ADC. The interface circuit is implemented by a 0.35 μm CMOS technology. The performance test of the TMR magnetic sensor system shows that: at a 5 V operating voltage, the sensor can achieve a power consumption of 120 mW, a full scale of ±1 Guass, a bias error of 0.01% full scale (FS), a nonlinearity of x-axis 0.13% FS, y-axis 0.11% FS, z-axis 0.15% FS and a noise density of x-axis 250 pT/Hz^1/2 (at 1 Hz), y-axis 240 pT/Hz^1/2 (at 1 Hz), z-axis 250 pT/Hz^1/2 (at 1 Hz), respectively. This work has a less power consumption, a smaller size, and higher resolution than other miniaturized magnetometers by comparison.

Micro-electromechanical system (MEMS) accelerometers are widely used in the inertial navigation and nanosatellites field. A high-performance digital interface circuit for a high-Q MEMS micro-accelerometer is presented in this work. The mechanical noise of the MEMS accelerometer is decreased by the application of a vacuum-packaged sensitive element. The quantization noise in the baseband of the interface circuit is greatly suppressed by a 4th-order loop shaping. The digital output is attained by the interface circuit based on a low-noise front-end charge-amplifier and a 4th-order Sigma-Delta (ΣΔ) modulator. The stability of high-order ΣΔ was studied by the root locus method. The gain of the integrators was reduced by using the proportional scaling technique. The low-noise front-end detection circuit was proposed with the correlated double sampling (CDS) technique to eliminate the 1/f noise and offset. The digital interface circuit was implemented by 0.35 μm complementary metal-oxide-semiconductor (CMOS) technology. The high-performance digital accelerometer system was implemented by double chip integration and the active interface circuit area was about 3.3 mm × 3.5 mm. The high-Q MEMS accelerometer system consumed 10 mW from a single 5 V supply at a sampling frequency of 250 kHz. The micro-accelerometer system could achieve a third harmonic distortion of −98 dB and an average noise floor in low-frequency range of less than −140 dBV; a resolution of 0.48 μg/Hz^1/2 (@300 Hz); a bias stability of 18 μg by the Allen variance program in MATLAB.

As a highly automated carrying vehicle, an automated guided vehicle (AGV) has been widely applied in various industrial areas. The collision avoidance of AGV is always a problem in factories. Current solutions such as inertial and laser guiding have low flexibility and high environmental requirements. An INS (inertial navigation system)-UWB (ultra-wide band) based AGV collision avoidance system is introduced to improve the safety and flexibility of AGV in factories. An electronic map of the factory is established and the UWB anchor nodes are deployed in order to realize an accurate positioning. The extended Kalman filter (EKF) scheme that combines UWB with INS data is used to improve the localization accuracy. The current location of AGV and its motion state data are used to predict its next position, decrease the effect of control delay of AGV and avoid collisions among AGVs. Finally, experiments are given to show that the EKF scheme can get accurate position estimation and the collisions among AGVs can be detected and avoided in time.

Placement has always been the most time-consuming part of the FPGA compilation flow. Conventional simulated annealing has been unable to keep pace with ever increasing sizes of designs and FPGA chip resources. Without utilizing information of the circuit topology, it relies on large amounts of random swap operations, which are time-costly. This paper proposes an adaptive range-based algorithm to improve the behavior of swap operations and limit the swap distances by introducing the concept of range-limiting strategy for nets. It avoids unnecessary design space exploration, and thus can converge to near-optimal solutions much more quickly. The experimental results are based on the Titan benchmarks, which contain 4K to 30K blocks, including LABs, IOs, DSPs and RAMs. This approach achieves 2.82X speed up, 4.8% reduction on wire length, 4.1% improvement on critical path compared with the SA from VTR with wire length-driven optimization, and 1.78X speed up, 10% reduction on wire length, 2% reduction on critical path with path timing-driven optimization. It also manifests better scalability on larger benchmarks.

This paper proposes the realization of dual-threshold independent-gate FinFETs by optimizing the FinFET process parameters including the electrode work function, silicon body thickness, and oxide thickness. The optimum values of the FinFET process parameters are derived using BSIM-IMG SPICE model for independent-gate FinFET devices. In optimum dual-threshold independent-gate (IG) FinFETs, a high-threshold IG FinFET is logically equivalent to two short-gate (SG) FinFETs in series, while a low-threshold one is logically equivalent to two SG FinFETs in parallel. The complementary static logic circuits and differential cascode voltage switch logic circuits based on the proposed IG FinFET devices have been verified. The results show that basic gates using the proposed dual-threshold independent-gate FinFETs obtain lower energy delay products than those implementations based on SG FinFETs.