This paper presents a novel architecture for in-memory computation of binary neural network (BNN) workloads based on STT-MRAM arrays. In the proposed architecture, BNN inputs are fed through bitlines, then, a BNN vector multiplication can be done by single sensing of the merged SL voltage of a row. Our design allows to perform unrestricted accumulation across rows for full utilization of the array and BNN model scalability, and overcomes challenges on the sensing circuit due to the limitation of low regular tunneling magnetoresistance ratio (TMR) in STT-MRAM. Circuit techniques are introduced in the periphery to make the energy-speed-area-robustness tradeoff more favorable. In particular, time-based sensing (TBS) and boosting are introduced to enhance the accuracy of the BNN computations. System simulations show 80.01% (98.42%) accuracy under the CIFAR-10 (MNIST) dataset under the effect of local and global process variations, corresponding to an 8.59% (0.38%) accuracy loss compared to the original BNN software implementation, while achieving an energy efficiency of 311 TOPS/W.

This paper introduces the concept of time-based sensing (TBS) for bitcell read in spin transfer torque magnetic RAMs arrays. The TBS scheme converts the bitline voltage into time, then the sense amplifier discriminates the two bitcell levels in the time domain. The TBS scheme substantially improves the read yield compared to conventional voltage sensing (CVS). As further advantage, TBS requires no analog reference generation and distribution by leveraging the implicit timing reference set by the gate delay in the sense amplifier. Monte Carlo simulations in 65 nm show that the proposed TBS improves the read bit error rate (BER) by two-three orders of magnitude, compared to CVS. This is achieved at the cost of less than 1% area penalty and 13-14% performance degradation, and insignificant (2%) energy penalty when designed at iso-area (minimum delay). Compared to other sensing schemes at iso-BER, the proposed TBS scheme achieves a more favorable area-robustness-energy-performance tradeoff.

This paper proposes a novel boosted voltage sensing (BVS) scheme that substantially improves the resiliency of STT-MRAMs against variations in read accesses based on bitline voltage sensing, and on a wide range of voltages. The BVS scheme mitigates the impact of variations in the senseamp and the reference voltage generation, and is based on switched-capacitor voltage boosters. The related area-performance-energy-resiliency tradeoff is explored, and design guidelines are derived to improve the read margin at minimum overhead.

This paper proposes a novel approach to enhance the STT-MRAMs read margin based on the concept of dynamic reference (DR). Our dynamic reference scheme dynamically adjusts the sense amplifier reference voltage according to the bitline voltage, aiming to widen the difference between the bitline and the reference voltage (i.e., the read margin). As a result, larger variations can be accommodated, thus improving the read robustness and substantially reducing the read failure rate. This DR scheme does not require any change in the bitcell and requires minimal modifications of conventional arrays, hence it can be jointly used with existing assist techniques enhancing the read robustness. From Monte Carlo simulations in 65 nm, the proposed DR scheme improves the read bit error rate by two orders of magnitude across a wide range of voltages (0.75-1.2 V) compared with the conventional voltage sensing scheme. This is achieved at 0.3% area overhead, less than 15% performance degradation, and less than 25% energy penalty. Furthermore, the joint adoption of the DR approach and switched-cap bitline boosting further reduces the sense amplifier area by 25% at iso-failure rate, and reduces the energy by 6-10% compared with the standalone DR.

This paper proposes an in-memory binary spiking neural network (BSNN) based on spin-transfer-torque magnetoresistive RAM (STT-MRAM). We propose residual BSNN learning using a surrogate gradient that shortens the time steps in the BSNN while maintaining sufficient accuracy. At the circuit level, presynaptic spikes are fed to memory units through differential bit lines (BLs), while binarized weights are stored in a subarray of nonvolatile STT-MRAM. When the common inputs are fed through BLs, vector-to-matrix multiplication can be performed in a single memory sensing phase, hence achieving massive parallelism with low power and low latency. We further introduce the concept of a dynamic threshold to reduce the implementation complexity of synapses and neuron circuitry. This adjustable threshold also permits a nonlinear batch normalization (BN) function to be incorporated into the integrate-and-fire (IF) neuron circuit. The circuitry greatly improves the overall performance and enables high regularity in circuit layouts. Our proposed netlist circuits are built on a 65-nm CMOS with a fitted magnetic tunnel junction (MTJ) model for performance evaluation. The hardware/software co-simulation results indicate that the proposed design can deliver a performance of 176.6 TOPS/W for an in-memory computing (IMC) subarray size of $1\times 288$ . The classification accuracy reaches 97.92% (83.85%) on the MNIST (CIFAR-10) dataset. The impacts of the device non-idealities and process variations are also thoroughly covered in the analysis.