Under radiation environment, conventional SRAMs suffer from high soft-error rate. To address this challenge, several radiation-hardened static-random access-memory (SRAM) cells such as twelve-transistor (12T) Dice and ten-transistor (10T) Quatro have been developed. Quatro is more promising since this cell delivers robust operation while incurring moderate area overhead. However, our study shows that Quatro experiences large number of write failures under parametric variations of scaled technologies, impeding the application of this SRAM cell. In this paper, we present a 12T SRAM cell named as we-Quatro. In spite of using more transistors, the proposed SRAM cell occupies essentially the same area as Quatro. Our extensive simulations show that the proposed cell provides good writability and comparable soft-error resilience to Quatro under parametric variations of 28-nm fully depleted SOI technology, validating the efficacy of our proposed we-Quatro.

This paper presents a novel architecture for in-memory computation of binary neural network (BNN) workloads based on STT-MRAM arrays. In the proposed architecture, BNN inputs are fed through bitlines, then, a BNN vector multiplication can be done by single sensing of the merged SL voltage of a row. Our design allows to perform unrestricted accumulation across rows for full utilization of the array and BNN model scalability, and overcomes challenges on the sensing circuit due to the limitation of low regular tunneling magnetoresistance ratio (TMR) in STT-MRAM. Circuit techniques are introduced in the periphery to make the energy-speed-area-robustness tradeoff more favorable. In particular, time-based sensing (TBS) and boosting are introduced to enhance the accuracy of the BNN computations. System simulations show 80.01% (98.42%) accuracy under the CIFAR-10 (MNIST) dataset under the effect of local and global process variations, corresponding to an 8.59% (0.38%) accuracy loss compared to the original BNN software implementation, while achieving an energy efficiency of 311 TOPS/W.

The total ionizing dose (TID) is a mechanism that threatens the reliability of transistors under radiation. In the literature, we found contradictory TID experimental results between device and circuit studies of fully depleted silicon-on-insulator (FD-SOI) technology. To resolve that conflict, we designed a special ring oscillator (RO) circuit in which the n-FET and p-FET gate-potentials can be programmed. The RO circuits were fabricated using 65-nm bulk-CMOS and 28-nm FD-SOI foundry baseline technologies and were dosed with ⁶⁰ Co gamma radiation up to 200 krad (SiO ₂ ). In addition, we measured drive current variations in the 28-nm FD-SOI after irradiation. Traditionally, there has been a belief that the TID of n-FETs is more dominant than that of p-FETs. However, we found that in FD-SOI, the TID effect of p-FET governs circuit performance degradation.

In this letter, we present a multibit static random-access memory computing-in-memory (CIM) macro with enhanced energy efficiency for edge devices tasking machine learning (ML) deep neural networks (DNNs). The proposed CIM macro computes matrix-vector multiplications (MVM) in an efficient “one-step” method reducing the energy consumption and control complexity. Furthermore, the proposed method computes not only the multiplications of a single weight but also the multibit weight with bit-shifting in the charge domain without the use of additional CMOS switches, thereby achieving very high energy efficiency. Measurement results in a 65-nm CMOS prototype chip show that it achieves the highest throughput of 204.8 GOPS at 1.2 V and 133.6 TOPS/W at 0.85 V.

In Space applications, the scaling of transistors has made integrated circuits (ICs) more susceptible to soft errors, caused by radiation strikes. When a soft error causes a bit flip in a memory device, this event is referred to as a Single Event Upset (SEU). Since SEU errors degrade system performance and eventually lead to system failure, the design of radiation-resilient memory is substantial. This paper presents a radiation resilient SRAM with a self-refresh scheme for lowering the number of errors in each row below a threshold number. The proposed self-refresh operation reads out the stored data and performs single error correction using a simple algorithm during its hold/idle mode. A 4KB SRAM test chip in 65nm CMOS technology demonstrates a significant reduction in errors with the self-refresh operation. When the SRAM test chip was exposed to accelerated proton radiation with an energy level of 39.38 MeV, the self-refresh scheme reduces the number of uncorrectable errors by 25× and 8× lesser for the fluence of 9.82 × 1011 particles/cm2 and 49.1 × 1011 particles/cm2, respectively.

With aggressive scaling down in integrated circuit technology, the design of double-node-upset (DNU)-resilient latches have become a major issue regarding radiation hardening by design (RHBD). The conventional DNU-resilient latches are mostly based on the Muller C-element (MCE) and the dual-interlocked storage cell (DICE) element, which exhibit severe limitations: charge sharing during the read operation at a system level and large power consumption. Overcoming these limitations, this brief proposes a DNU-resilient latch based on a novel latch element. The proposed latch fully exploits upset polarity awareness, achieving the maximum number of single-event upset (SEU)-insensitive nodes. We develop a novel double modular redundancy architecture for the DNU-resilient latch design with one SEU-immune module. Based on simulation results, the proposed latch achieves up to 27.6X average power-delay-area-product (PDAP) improvement over state-of-the-art DNU-resilient latches.