The heterogeneous data generated within IoMT environments have presented significant challenges in ML-based attack detection approaches, where the lack of standardized features creates a barrier. Current ML-based attack detection methods rely on feature extraction techniques, often requiring specialized security expertise to analyze and identify the most relevant features for modeling ML algorithms, hindering widespread adoption in IoMT. This study presents a new approach for detecting ransomware-spreading behavior based on Nilsimsa fingerprinting and Machine Learning to represent network traffic and detect infected network flows. The performance of our proposal was evaluated using two IoMT datasets, ICE and CICIoMT2024. Our approach demonstrated better performance than current ML-based attack detection methods using network traffic features in terms of precision, F1-score, and training efficiency across both datasets. The Random Forest algorithm modeled with Nilsimsa fingerprints on the ICE dataset achieved 100% precision and 98.72% F1-score. Similarly, on the CICIoMT2024 dataset, our approach exhibited 99.44% precision and 98.59% F1-score.

Currently, cryptographic algorithms are widely applied to communications systems to guarantee data security. For instance, in an emerging automotive environment where connectivity is a core part of autonomous and connected cars, it is essential to guarantee secure communications both inside and outside the vehicle. The AES algorithm has been widely applied to protect communications in onboard networks and outside the vehicle. Hardware implementations use techniques such as iterative, parallel, unrolled, and pipeline architectures. Nevertheless, the use of AES does not guarantee secure communication, because previous works have proved that implementations of secret key cryptosystems, such as AES, in hardware are sensitive to differential fault analysis. Moreover, it has been demonstrated that even a single fault during encryption or decryption could cause a large number of errors in encrypted or decrypted data. Although techniques such as iterative and parallel architectures have been explored for fault detection to protect AES encryption and decryption, it is necessary to explore other techniques such as pipelining. Furthermore, balancing a high throughput, reducing low power consumption, and using fewer hardware resources in the pipeline design are great challenges, and they are more difficult when considering fault detection and correction. In this research, we propose a novel hybrid pipeline hardware architecture focusing on error and fault detection for the AES cryptographic algorithm. The architecture is hybrid because it combines hardware and time redundancy through a pipeline structure, analyzing and balancing the critical path and distributing the processing elements within each stage. The main contribution is to present a pipeline structure for ciphering five times on the same data blocks, implementing a voting module to verify when an error occurs or when output has correct cipher data, optimizing the process, and using a decision tree to reduce the complexity of all combinations required for evaluating. The architecture is analyzed and implemented on several FPGA technologies, and it reports a throughput of 0.479 Gbps and an efficiency of 0.336 Mbps/LUT when a Virtex-7 is used.