This paper presents a delay-suppressed sliding mode observer (SMO) to observe the real-time rotor position of a permanent magnet synchronous machine (PMSM) controlled by vector control (VC) algorithms. Firstly, in order to solve the low pass filter (LPF) delay problem existing in the traditional signum function-based sliding mode observer (SMO), a brand-new hyperbolic function is initially selected as the switching function. Because a hyperbolic function with proper boundary layer is capable of reducing the chattering phenomenon of a SMO, it is not necessary to re-employ LPFs to eliminate the adverse impacts of chattering on the position estimation accuracy. In order to ensure the reachability and stability of the hyperbolic function-based SMO, the observer gain is calculated by the means of a Lyapunov function in this paper. Secondly, to solve the problem of calculation delay caused by digital computation, a current pre-compensation scheme based on dual-sampling strategy in one switching period is proposed. After compensating the calculation delay, the accuracy of position estimation as well as the motor control performance can be improved. Finally, the proposed SMOs with and without delay compensation are verified by both simulation and experiments which are conducted on a three-phase 1.5kW PMSM drive prototype.

This paper proposes a new finite control set model predictive control (FCS-MPC) strategy that simultaneously evaluates two targeting control objectives (TCOs) including speed and currents in a single cost function, achieving high-performance single-closed-loop control structure. Besides, aiming at the calculation delay problem of the MPC controllers, a novel calculation delay compensation method by predicting the current variation within the delay time is proposed. In this paper, an improved machine model that is specially designed for the multi-objective FCS-MPC operation is illustrated at first. Then, a new cost function which can evaluate the tracking performance of speed and d-axis current and steady-state performance of q-axis current is developed. Compared to the conventional FCS-MPC approaches, extra speed controllers are not needed so that the proposed control topology becomes simpler. Then, in order to tune the weighting factors for the speed and currents in the cost function, an efficient handling strategy containing two implementation procedures, state variable normalization (SVN) and balance of state sensitivity to voltage alteration, is developed. Finally, a brand-new computation delay estimation and compensation technique based on dual sampling within a switching period is proposed to reduce the current and torque ripples during control process. Comparative simulation and experiments are conducted on a three-phase 1.5kW PMSM drive system.

This paper addresses the transient current distribution in the multichip half-bridge power modules, where two types of paralleling connections with different current commutation mechanisms are considered: paralleling dies and paralleling half-bridges. It reveals that with paralleling dies, both the high side and low side paralleled devices experience a similar transient current imbalance due to the mismatched stray inductance. However, with paralleling half-bridges and with the same mismatched stray inductances, the high side paralleled devices have much smaller transient current imbalance, the cause of which is found be to the current commutation process. Theoretical analysis based on the circuit modeling and current commutation process elaborates the findings, which are then confirmed by experimental results.

With the increasing demand of applications that have two different output voltages, the single-input dual-output (SIDO) converter with fewer components is becoming the cost-effective option instead of employing two single-input single-output converters. However, the cross regulation of different outputs is still a challenge in SIDO converters design. To save cost and obtain improved cross regulation performance, a novel SIDO converter consisting of three active switches is proposed in this paper. Owing to the use of a voltage multiplier circuit, a high step-up voltage conversion ratio is achieved with relatively low voltage stress of switches. Thanks to the independent power flow and two control variables, the cross regulation performance is improved, and simultaneous buck as well as boost output voltages are realized. Additionally, all switches can achieve zero-voltage switching operation, which contributes to a significant switching loss reduction. The operation characteristics, design considerations, and control strategy of the proposed converter are analyzed. To verify the theoretical analysis and measure the power efficiency, a prototype circuit with 48V input and 24V/2A, 200V/1A outputs is built.

A state-of-the-art 3.3-kV/450-A hybrid power module for the next generation traction inverter of rolling stock is reported in this paper, combining the Si IGBT and SiC SBD chips. Compared with the existing hybrid technology at the same voltage level, this module is characterized by a half-bridge topology, in which 6 IGBT and 12 SBD chips are integrated in each switch. The outnumbering of the diodes represents a promising mitigation to the low availability of SBDs at this voltage level. Both static and dynamic test of this module and an equivalent Si-based module are carried out comparatively. Apart from describing the features of compactness, low-inductance and good current distribution among chips, this module is characterized by low turn-on current overshooting and turn-on loss of IGBTs, negligible diode reverse recovery time and loss, as well as flexible allowance of IGBT turn-on current rising rate dI/dt. A parameterized study is carried out to benchmark the advantage of this new topology. Based on the experimental results, the performance of the hybrid module in a three-phase traction inverter circuit is also evaluated by means of electro-thermal simulation. The hybrid module distinguishes itself by describing much lower power loss and junction temperature than its Si-based counterpart.

A method to derive the junction-to-case level coupling thermal resistances among paralleling chips in the multichip semiconductor power module has been proposed in this article. It is revealed that the traditional structure function methodology (SFM), which is developed for analyzing the self-heating effect of the driving-point chip, cannot be applied directly in the thermal coupling analysis, where the influence of the driving-point chip on the neighboring acceptor chip is concerned. This article shows that by combining the traditional SFM with the frequency-domain analysis (FDA), the effective separation points between the module case and the external cooling setup can be identified in both time and frequency domains, which correspond to the characteristic frequency points in the complex loci of the thermal impedance curves. By extracting the amplitudes at the characteristic frequencies from the complex loci in the FDA, the junction-to-case level coupling thermal resistances can be derived. Both simulation and experimental study have been carried out to verify the concept. The agreement between the two justifies the proposed method.