In pursuit of high power density and high reliability of power converters, the junction temperature of power devices becomes an essential indicator for heath condition monitoring and thermal management. Particularly under high-temperature operating conditions, the temperature-dependent thermal properties of the chip and ceramic materials must be incorporated to enhance the prediction accuracy. In this article, an improved temperature-dependent Cauer-type thermal network of insulated-gate bipolar transistor (IGBT) module is established. The temperature dependence of thermal parameters for the chip layer and ceramic layer is meticulously considered. More importantly, finite-element method (FEM) simulation is used to yield the heat flux curve of the power module at the center line in order to better imitate the real heat-spreading scenario. In this way, the effective heat transfer area of each layer can be calculated accurately and analytically. By this analytic method, the temperature-dependent thermal impedance can be efficiently determined. Compared with prior-art fully FEM-based temperature-dependent thermal impedance characterization method, the method proposed in this article reduces the FEM simulation time cost approximately 20 times under the same computing hardware facilities and considerably simplifies the parameter extraction process. Finally, experimental results based on two commercial IGBT modules successfully validate the usefulness, effectiveness, and accuracy of the proposed thermal network model.

Of great significance is knowledge of failure modes of IGBT modules under power cycling test (PCT) in advance. It can not only precisely determine accurate utilization of physics-of-failure lifetime prediction methods but also help optimize IGBT designs. However, establishing an accurate and generic offline failure mode classification method for different IGBT modules remains a challenging problem due to the complex degradation process of IGBT modules. In this article, a data-driven convolutional neural network (CNN) based method is proposed for quad-classification of failure modes for different IGBT modules under different PCT conditions. First, in order to accurately characterize the mapping between the failure modes and the precursor parameters, a framework of precursor parameters is meticulously established. Then, mainly using collected training data from existing publications, the CNN classification model is developed by a newly dynamic tuning-multilevel particle swarm-back propagation optimization algorithm. Finally, experimental PCTs of various IGBT modules are performed. The obtained PCT data and additional testing data from existing publications are used to verify the generalizability and robustness of the proposed classification method. The superiority of the proposed method is well demonstrated through comparison with random CNN, the state-of-the-art particle swarm optimization CNN, and other intelligent algorithms.

SiC MOSFETs have received great attention due to their excellent electrothermal properties. Accurate junction temperature information of SiC MOSFETs ensures safe operation and helps effective thermal management. However, the existing thermal models have limits to correctly predict the thermal behaviors, whose parameter extraction processes are normally complicated. Most of the thermal models generally omit the temperature effects, which greatly impairs their usefulness and effectiveness. Here, a temperature-dependent physical resistor–capacitor ( RC ) network model is proposed, which can accurately characterize the thermal behavior of SiC MOSFETs particularly under high-temperature conditions. Meanwhile, the boundary conditions are fully investigated and modeled, which guarantees the adaptation of the proposed model for different real-field applications. The proposed method can remarkably simplify the process of parameter extraction since only the steady-state temperature distribution information is required with the assistance of finite-element method (FEM). Finally, the effectiveness and the robustness of the proposed model are validated by FEM simulation and experiments.

Remaining useful lifetime (RUL) prediction for lift-off of bond wires in IGBT modules is essential to avoid strenuous periodic maintenance and electrical accidents of IGBT-based power converters. However, existing model-driven RUL methods mostly focus on lift-off of the first bond wire and rarely consider on-chip temperature distribution, which result in low prediction accuracy. Herein, a novel prognostic method for bond wire lift-off failure in IGBT considers uneven on-chip temperature distribution during crack propagation at the bond-metallization interface (BMI), which fulfills improved prediction error for RUL. In this method, a wire-bond contact degradation model is built according to the on-chip temperature distribution. The number of power cycles as a function of the crack length and temperature swing of BMI is determined by finite element analysis and power cycling test. In this way, the equivalent resistance reflecting crack propagation at BMI can be accurately estimated, and the degradation curve of the ON-state voltage (Vce_on) can be predicted to yield RUL under the widely-acknowledged failure criteria of bond wire. The effectiveness and generalization of the proposed method are validated by additional tests and show great superiority to the prior-art condition-based RUL prediction methods.

Creep plays a significant role in the deterioration of solder layers particularly over extended periods of heating, even though numerous existing studies focused on the mechanism of fatigue failure. In this article, the creep-fatigue interaction failure mechanism of the solder layer under power cycling test (PCT) is investigated. The microstructure of solder layer was successively scanned using an ultrahigh resolution computed tomography scanner to observe the degradation of the microstructure. It is found that the microstructure of the solder layer had obvious changes even when the thermal resistance remains unchanged. The initial voids in the solder layer are constantly collapsing and new voids are constantly growing out. This is different from the previous finding that the solder layer degrades by cracks initiating and propagating under short heating in PCT. The reason for this result is that creep becomes the dominant factor in the degradation of solder layer. Scanning electron microscope (SEM) scanning of the solder layer after failure showed that microcracks also existed, but their distribution was more dispersed, making it difficult to determine their crack initiation locations and propagation paths. Therefore, the failure of the solder layer under longer heating period and higher temperatures is considered to be a complex creep-fatigue interaction failure process. Finally, a thermal resistance degradation model is proposed, which can accurately predict the change of the thermal resistance during module degradation.