Valerio Tenace

Dr. Valerio Tenace

Department of Electrical and Computer Engineering, University of Utah, Salt Lake City, UT 84112, USA

Research Focus & Metrics

Academic Career Length

12Years (2015-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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24 June 2020 in Cancers
Verified
Journal Article
Open access
PDF file
VGValentina Gaidano
Valentina Gaidano
VTValerio Tenace
Valerio Tenace
NSNathalie Santoro
Nathalie Santoro
SVSilvia Varvello
Silvia Varvello
ACAlessandro Cignetti
Alessandro Cignetti
MGMassimo Geuna
Massimo Geuna
The immunophenotype is a key element to classify B-cell Non-Hodgkin Lymphomas (B-NHL); while it is routinely obtained through immunohistochemistry, the use of flow cytometry (FC) could bear several advantages. However, few FC laboratories can rely on a long-standing practical experience, and the literature in support is still limited; as a result, the use of FC is generally restricted to the analysis of lymphomas with bone marrow or peripheral blood involvement. In this work, we applied machine learning to our database of 1465 B-NHL samples from different sources, building four artificial predictive systems which could classify B-NHL in up to nine of the most common clinico-pathological entities. Our best model shows an overall accuracy of 92.68%, a mean sensitivity of 88.54% and a mean specificity of 98.77%. Beyond the clinical applicability, our models demonstrate (i) the strong discriminatory power of MIB1 and Bcl2, whose integration in the predictive model significantly increased the performance of the algorithm; (ii) the potential usefulness of some non-canonical markers in categorizing B-NHL; and (iii) that FC markers should not be described as strictly positive or negative according to fixed thresholds, but they rather correlate with different B-NHL depending on their level of expression.

28 February 2021 in Cancers
Verified
Journal Article
Open access
PDF file
VGValentina Gaidano
Valentina Gaidano
MHmohammad houshmand
mohammad houshmand
NVnicoletta vitale
nicoletta vitale
GCGiovanna Carrá
Giovanna Carrá
Alessandro MorottiAlessandro Morotti
Alessandro Morotti
PCPaola Circosta
Paola Circosta
Dihydroorotate Dehydrogenase (DHODH) is a key enzyme of the de novo pyrimidine biosynthesis, whose inhibition can induce differentiation and apoptosis in acute myeloid leukemia (AML). DHODH inhibitors had shown promising in vitro and in vivo activity on solid tumors, but their effectiveness was not confirmed in clinical trials, probably because cancer cells exploited the pyrimidine salvage pathway to survive. Here, we investigated the antileukemic activity of MEDS433, the DHODH inhibitor developed by our group, against AML. Learning from previous failures, we mimicked human conditions (performing experiments in the presence of physiological uridine plasma levels) and looked for synergic combinations to boost apoptosis, including classical antileukemic drugs and dipyridamole, a blocker of the pyrimidine salvage pathway. MEDS433 induced apoptosis in multiple AML cell lines, not only as a consequence of differentiation, but also directly. Its combination with antileukemic agents further increased the apoptotic rate, but when experiments were performed in the presence of physiological uridine concentrations, results were less impressive. Conversely, the combination of MEDS433 with dipyridamole induced metabolic lethality and differentiation in all AML cell lines; this extraordinary synergism was confirmed on AML primary cells with different genetic backgrounds and was unaffected by physiological uridine concentrations, predicting in human activity.

1 February 2021
Verified
Conference Paper
Open access
SRShubham Rai
Shubham Rai
WNWalter Lau Neto
Walter Lau Neto
YMYukio Miyasaka
Yukio Miyasaka
XZXinpei Zhang
Xinpei Zhang
MYMingfei Yu
Mingfei Yu
SCSatrajit Chatterjee
Satrajit Chatterjee
Logic synthesis is a fundamental step in hardware design whose goal is to find structural representations of Boolean functions while minimizing delay and area. If the function is completely-specified, the implementation accurately represents the function. If the function is incompletely-specified, the implementation has to be true only on the care set. While most of the algorithms in logic synthesis rely on SAT and Boolean methods to exactly implement the care set, we investigate learning in logic synthesis, attempting to trade exactness for generalization. This work is directly related to machine learning where the care set is the training set and the implementation is expected to generalize on a validation set. We present learning incompletely-specified functions based on the results of a competition conducted at IWLS 2020. The goal of the competition was to implement 100 functions given by a set of care minterms for training, while testing the implementation using a set of validation minterms sampled from the same function. We make this benchmark suite available and offer a detailed comparative analysis of the different approaches to learning.

28 December 2018 in Future Internet
Verified
Journal Article
Open access
PDF file
MGMatteo Grimaldi
Matteo Grimaldi
VTValerio Tenace
Valerio Tenace
ANDREA CALIMERAANDREA CALIMERA
ANDREA CALIMERA
Convolutional Neural Networks (CNNs) are brain-inspired computational models designed to recognize patterns. Recent advances demonstrate that CNNs are able to achieve, and often exceed, human capabilities in many application domains. Made of several millions of parameters, even the simplest CNN shows large model size. This characteristic is a serious concern for the deployment on resource-constrained embedded-systems, where compression stages are needed to meet the stringent hardware constraints. In this paper, we introduce a novel accuracy-driven compressive training algorithm. It consists of a two-stage flow: first, layers are sorted by means of heuristic rules according to their significance; second, a modified stochastic gradient descent optimization is applied on less significant layers such that their representation is collapsed into a constrained subspace. Experimental results demonstrate that our approach achieves remarkable compression rates with low accuracy loss (<1%).

1 November 2015 in Microprocessors and Microsystems
Verified
Journal Article
Open access
SMSandeep Miryala
Sandeep Miryala
VTValerio Tenace
Valerio Tenace
ANDREA CALIMERAANDREA CALIMERA
ANDREA CALIMERA
EMEnrico Macii
Enrico Macii
Massimo PoncinoMassimo Poncino
Massimo Poncino
Recent works have proven the functionality of electrostatically controlled graphene p-n junctions that can serve as basic primitive for the implementation of a new class of compact graphene-based reconfigurable multiplexer logic gates. Those gates, referred as RG-MUXes, while having higher expressive power and better performance w.r.t. standard CMOS gates, they also have the drawback of being intrinsically less power/energy efficient. In this work we address this problem from a circuit perspective, namely, we revisit RG-MUXes as devices that can operate adiabatically and hence with ultra-low (ideally, almost zero) power consumption. More specifically, we show how to build basic logic gates and, eventually, more complex logic functions, by appropriately interconnecting graphene-based p-n junctions as to implement the adiabatic charging principle. We provide a comparison in terms of power and performance against both adiabatic CMOS and their non-adiabatic graphene-based counterparts; characterization results collected from SPICE simulations on a set of representative functions show that the proposed ultra-low power graphene circuits can operate with 1.5-4 orders of magnitude less average power w.r.t. adiabatic CMOS and non-adiabatic graphene counterparts respectively. When it comes to performance, adiabatic graphene shows 1.3 (w.r.t. adiabatic CMOS) to 4.5 orders of magnitude (w.r.t. non-adiabatic technologies) better power-delay produc

1 October 2018
Verified
Conference Paper
Closed access
VTValerio Tenace
Valerio Tenace
ANDREA CALIMERAANDREA CALIMERA
ANDREA CALIMERA
Machine learning (ML) theories and tools suggest alternative forms to conceive and represent relationships among data. The same theories find their application in the Boolean domain, where logic functions can be described as inference rules. This paper introduces Inferential Logic, a novel paradigm that leverages the ML concept of statistical inference for the design of combinational logic circuits, the Inferential Logic Circuits (ILCs). This new design concept is conceived for low-power circuits that run quasi-exact computation in error-resilient applications, but it also provides an exact run-mode that can be dynamically enabled when accuracy scaling is not an option.