With the growing popularity of cryptocurrencies, which are an important part of day-to-day transactions over the Internet, the interest in being part of the so-called cryptomining service has attracted the attention of investors who wish to quickly earn profits by computing powerful transactional records towards the blockchain network. Since most users cannot afford the cost of specialized or standardized hardware for mining purposes, new techniques have been developed to make the latter easier, minimizing the computational cost required. Developers of large cryptocurrency houses have made available executable binaries and mainly browser-side scripts in order to authoritatively tap into users’ collective resources and effectively complete the calculation of puzzles to complete a proof of work. However, malicious actors have taken advantage of this capability to insert malicious scripts and illegally mine data without the user’s knowledge. This cyber-attack, also known as cryptojacking, is stealthy and difficult to analyze, whereby, solutions based on anti-malware extensions, blocklists, JavaScript disabling, among others, are not sufficient for accurate detection, creating a gap in multi-layer security mechanisms. Although in the state-of-the-art there are alternative solutions, mainly using machine learning techniques, one of the important issues to be solved is still the correct characterization of network and host samples, in the face of the increasing escalation of new tampering or obfuscation techniques. This paper develops a method that performs a fingerprinting technique to detect possible malicious sites, which are then characterized by an autoencoding algorithm that preserves the best information of the infection traces, thus, maximizing the classification power by means of a deep dense neural network.

Nowadays, the design of ultra-compact area advanced encryption standard (AES) architectures is highly demanded by the electronics industry since many of these architectures are embedded in portable devices, such as smart phones, tablets, etc., in which the area is critically limited. Until now, many approaches have been proposed to create high-processing and compact architectures. However, the area consumption is still a factor to be improved. In this paper, a highly compact encryption/decryption architecture, which is implemented in a low-cost FPGA, to efficiently simulate the AES algorithm, is proposed. Specifically, an optimized Galois Field Multiplier, which is the most demanding operation in terms of area consumption and processing speed, involved in Mix-Columns and Inverse Mix-Columns transformations, is presented. Therefore, the optimization of the proposed GF (28) multiplier by two has allowed to us create an ultra-compact Mix-Columns circuit since this circuit involves large number of multiplications. In addition, the design involves a routing circuit which allowed the proposed architecture to perform encryption or decryption by using common modules. The results demonstrate that the proposed digital circuit expends fewer LUTs and fewer registers when compared with the most compact encryption/decryption architectures reported to date.

The use of Inductive Wireless Power Transfer (IWPT) varies from low-power applications such as mobile phones and tablets chargers to high-power electric vehicles chargers. DC–DC converters are used in IWPT systems, and their design needs to consider the demand of high efficiency in the power transfer. In this paper, a DC–DC power converter for IWPT is proposed. Its topology uses a DC–AC converter in the transmitter circuit and an AC–DC converter in the receptor. The transmitter has an interleaved coupled-Buck converter that integrates two Buck converters connected to a half inverter bridge and a parallel resonant load. The control strategy implemented for the semiconductor switching devices allows two operating modes to obtain a sinusoidal output voltage with a low distortion that makes it suitable in high-efficiency power transfer systems. To obtain a DC output voltage, a full wave bridge rectifier is used in the receptor circuit. The proposed topology and the control strategy are validated with simulation and experimental results for a 15 W prototype.