Nowadays, the design of ultra-compact area advanced encryption standard (AES) architectures is highly demanded by the electronics industry since many of these architectures are embedded in portable devices, such as smart phones, tablets, etc., in which the area is critically limited. Until now, many approaches have been proposed to create high-processing and compact architectures. However, the area consumption is still a factor to be improved. In this paper, a highly compact encryption/decryption architecture, which is implemented in a low-cost FPGA, to efficiently simulate the AES algorithm, is proposed. Specifically, an optimized Galois Field Multiplier, which is the most demanding operation in terms of area consumption and processing speed, involved in Mix-Columns and Inverse Mix-Columns transformations, is presented. Therefore, the optimization of the proposed GF (28) multiplier by two has allowed to us create an ultra-compact Mix-Columns circuit since this circuit involves large number of multiplications. In addition, the design involves a routing circuit which allowed the proposed architecture to perform encryption or decryption by using common modules. The results demonstrate that the proposed digital circuit expends fewer LUTs and fewer registers when compared with the most compact encryption/decryption architectures reported to date.

Over the last decade, dual active bridge (DAB) converters have become critical components in high-frequency power conversion systems. Recently, intensive efforts have been directed at optimizing DAB converter design and control. In particular, several strategies have been proposed to improve the performance of DAB control systems. For example, fractional-order (FO) control methods have proven potential in several applications since they offer improved controllability, flexibility, and robustness. However, the FO controller design process is critical for industrializing their use. Conventional FO control design methods use frequency domain-based design schemes, which result in complex and impractical designs. In addition, several nonlinear equations need to be solved to determine the optimum parameters. Currently, metaheuristic algorithms are used to design FO controllers due to their effectiveness in improving system performance and their ability to simultaneously tune possible design parameters. Moreover, metaheuristic algorithms do not require precise and detailed knowledge of the controlled system model. In this paper, a hybrid algorithm based on the chaotic artificial ecosystem-based optimization (AEO) and manta-ray foraging optimization (MRFO) algorithms is proposed with the aim of combining the best features of each. Unlike the conventional MRFO method, the newly proposed hybrid AEO-CMRFO algorithm enables the use of chaotic maps and weighting factors. Moreover, the AEO and CMRFO hybridization process enables better convergence performance and the avoidance of local optima. Therefore, superior FO controller performance was achieved compared to traditional control design methods and other studied metaheuristic algorithms. An exhaustive study is provided, and the proposed control method was compared with traditional control methods to verify its advantages and superiority.

Nowadays, image steganography has an important role in hiding information in advanced applications, such as medical image communication, confidential communication and secret data storing, protection of data alteration, access control system for digital content distribution and media database systems. In these applications, one of the most important aspects is to hide information in a cover image whithout suffering any alteration. Currently, all existing approaches used to hide a secret message in a cover image produce some level of distortion in this image. Although these levels of distortion present acceptable PSNR values, this causes minimal visual degradation that can be detected by steganalysis techniques. In this work, we propose a steganographic method based on a genetic algorithm to improve the PSNR level reduction. To achieve this aim, the proposed algorithm requires a private key composed of two values. The first value serves as a seed to generate the random values required on the genetic algorithm, and the second value represents the sequence of bit locations of the secret medical image within the cover image. At least the seed must be shared by a secure communication channel. The results demonstrate that the proposed method exhibits higher capacity in terms of PNSR level compared with existing works.

Finite-field arithmetic operations are vital for the computation of complex cryptography algorithms used in several cutting-edge applications, such as side-channel attacks, authentication, digital signatures, among others. Currently, the simulation of these algorithms exceeds the computational capabilities of conventional computing systems. This aspect becomes critical, especially when these algorithms are implemented in resource-constrained electronic appliances. In particular, the improvement of execution time in these devices generally require more area. To overcome this issue, a large number of works have been focused on the development of compact conventional binary finite-field arithmetic circuits over GF(p) since these demand a large area consumption. Inspired by neural phenomena, a new emerging branch of computer science has made intensive efforts to improve area consumption of conventional arithmetic circuits. However, the development of compact finite-field arithmetic circuits over GF(p) is a still a challenging task. In this work, we present for the first time, the design of four new finite-field arithmetic circuits over GF(p) based on spiking neural P (SN P) systems with communication on request. In addition, we propose a neural processor to perform four new finite-field arithmetic operations over GF(p) by using the same processing core, which is not feasible with the use of conventional binary circuits since each finite-field arithmetic-binary circuit over GF(p) is implemented separately, to significantly improve the area consumption. This has mainly been achieved since the neural processor dynamically change its configuration, which is defined in terms of the connectivity and firing rules of each neuron.

Nowadays, high-performance audio communication devices demand superior audio quality. To improve the audio quality, several authors have developed acoustic echo cancellers based on particle swarm optimization algorithms (PSO). However, its performance is reduced significantly since the PSO algorithm suffers from premature convergence. To overcome this issue, we propose a new variant of the PSO algorithm based on the Markovian switching technique. Furthermore, the proposed algorithm has a mechanism to dynamically adjust the population size over the filtering process. In this way, the proposed algorithm exhibits great performance by reducing its computational cost significantly. To adequately implement the proposed algorithm in a Stratix IV GX EP4SGX530 FPGA, we present for the first time, the development of a parallel metaheuristic processor, in which each processing core simulates the different number of particles by using the time-multiplexing technique. In this way, the variation of the size of the population can be effective. Therefore, the properties of the proposed algorithm along with the proposed parallel hardware architecture potentially allow the development of high-performance acoustic echo canceller (AEC) systems.