Spiking Neural Networks (SNN) for Versatile Applications (SNAVA) simulation platform is a scalable and programmable parallel architecture that supports real-time, large-scale, multi-model SNN computation. This parallel architecture is implemented in modern Field-Programmable Gate Arrays (FPGAs) devices to provide high performance execution and flexibility to support large-scale SNN models. Flexibility is defined in terms of programmability, which allows easy synapse and neuron implementation. This has been achieved by using a special-purpose Processing Elements (PEs) for computing SNNs, and analyzing and customizing the instruction set according to the processing needs to achieve maximum performance with minimum resources. The parallel architecture is interfaced with customized Graphical User Interfaces (GUIs) to configure the SNN's connectivity, to compile the neuron-synapse model and to monitor SNN's activity. Our contribution intends to provide a tool that allows to prototype SNNs faster than on CPU/GPU architectures but significantly cheaper than fabricating a customized neuromorphic chip. This could be potentially valuable to the computational neuroscience and neuromorphic engineering communities.

During the last decade, an emerging branch of computer science (biologically inspired engineering) has been made intensive studies to create an efficient CPU based on spiking neural P systems. Most of these studies have been focused on developing theoretical neural arithmetic circuits that could be integrated into an arithmetic logic unit. However, the memory system has a significant relevance since modern computers demand large memory bandwidth affecting significantly their performance and power consumption. Recently, the use of memory processing units (MPUs) allows to increase their performance by processing and storing the data in the same unit. This work maybe considered as a first step toward the design of a memory system highly inspired by the neural processing of the soma, dendritic behaviour and astrocyte‐like control. In addition, the basic neural single neural (SN) P memory cells can compute intrinsically two basic arithmetic operations (addition and subtraction) that potentially allow the development of a neural MPU system without modifying the basic structure of the neural SN P memory cell. High definition video processing is one of the potential applications to apply the proposed neural MPU to increase the processing speed compared with existing approaches.

Affine projection (AP) algorithms have demonstrated faster convergence speed than conventional least mean square (LMS) algorithms, thus providing an attractive solution in the active noise control (ANC) field. However, the AP algorithms demand high computational cost, restricting their practical use in real-time ANC applications. Recently, a multichannel filtered-x error-coded affine projection-like (FXECAP-L) algorithm with evolving order has been proposed to reduce the computational burden by maintaining the convergence speed of AP algorithms. In order to obtain an efficient and robust FXECAP-L algorithm with evolving order, the scaling factor and encoder resolution need to be adjusted manually, which is a time-consuming and costly effort that must be carried out by expert designers. To reduce these costs and efforts, we introduce, for the first time, a strategy for automatic adjustment of the scaling factor and encoder resolution that benefits the rapid development of practical ANC applications. To demonstrate its practical use, we applied the proposed strategy for controlling the noise in an acoustic duct. The practical results demonstrate the automatic adjustment of the FXECAP-L algorithm which maintains high convergence speed at the expense of a small compromise in terms of processing time.