We present and experimentally validate two minimal compact memristive models for spiking neuronal signal generation using commercially available low-cost components. The first neuron model is called the Memristive Integrate-and-Fire (MIF) model, for neuronal signaling with two voltage levels: the spike-peak, and the rest-potential. The second model MIF2 is also presented, which promotes local adaptation by accounting for a third refractory voltage level during hyperpolarization. We show both compact models are minimal in terms of the number of circuit elements and integration area. Using the MIF and MIF2 models, we postulate the design of a memristive solid-state brain with an estimation of its surface area and power consumption. Analytical projections show that a memristive solid-state brain could be realized within (i) the surface area of the median human brain, 2,400cm ² , (ii) the same volume of the median human brain, and (iii) a total power budget of approximately 20 W using a 3.5 nm technology. Distinct from the past decade of memristive neuron literature, our benchmarks are attained using generic commercially available memristors that are reproducible using off-the-shelf components. We expect this work can promote more experimental demonstrations of memristive circuits that do not rely on prohibitively expensive fabrication processes.

This paper proposes CMOS synapse and neuron for use in spiking neural networks to perform cognitive functions in a bio-inspired manner. The proposed synapse can trace the eligibility of the timing relationship between pre- and post-synaptic spikes, supporting a bio-plausible local learning rule called the spike timing-dependent plasticity (STDP) in an energy- and area-efficient manner. The proposed neuron can support neural functions such as synaptic current integration, threshold-based firing, neuronal leaking, membrane potential resetting, and adjustable refractory period with improved energy and area efficiency. The STDP curve shape of the synapse and the firing rate of the neuron can be adjusted as desired. Their variability due to process, voltage, and temperature (PVT) variations can also be minimized. The proposed CMOS neuron and synapse circuits were designed in a 28-nm CMOS process. The performance evaluation results indicate that the proposed synapse reduces energy consumption and area by up to 94% and 43% compared to conventional CMOS synapses. They also indicate that the proposed neuron achieves energy and area reductions of 37% and 23%, respectively, compared to conventional CMOS neurons. An associative neural network composed of the proposed neuron and synapse was designed to verify that they together work well for performing a cognitive function of associative learning and inferencing.

This brief proposes a pulse-width modulation buck converter with an active ramp tracking control to achieve a fast load transient response. When the difference between the output voltage and reference voltage is increased to a certain level in the load transient situation, the ramp bias voltages track the error voltage and provide a full duty to power switches. This helps restore the output voltage to the reference voltage, improving the load transient response speed and decreasing the overshoot/undershoot and their recovery times at the output voltage. A test chip was fabricated in a 65-nm CMOS technology, whose performance evaluation results indicated that the proposed buck converter reduced overshoot/undershoot at the output by up to 61.1% and the recovery time by up to 60.0% for a 450-mA load current step. The maximum power conversion efficiency of the proposed converter is 92.0% for 3.3 V input voltage and 1.8 V output voltage.

We present, in this paper, a new 10T static random access memory cell having single ended decoupled read-bitline (RBL) with a 4T read port for low power operation and leakage reduction. The RBL is precharged at half the cell's supply voltage, and is allowed to charge and discharge according to the stored data bit. An inverter, driven by the complementary data node (QB), connects the RBL to the virtual power rails through a transmission gate during the read operation. RBL increases toward the V _DD level for a read-1, and discharges toward the ground level for a read-0. Virtual power rails have the same value of the RBL precharging level during the write and the hold mode, and are connected to true supply levels only during the read operation. Dynamic control of virtual rails substantially reduces the RBL leakage. The proposed 10T cell in a commercial 65 nm technology is 2.47× the size of 6T with β = 2, provides 2.3× read static noise margin, and reduces the read power dissipation by 50% than that of 6T. The value of RBL leakage is reduced by more than 3 orders of magnitude and (I _ON/ I _OFF) is greatly improved compared with the 6T BL leakage. The overall leakage characteristics of 6T and 10T are similar, and competitive performance is achieved.

A CMOS charge pump based on a transfer blocking technique and a modified precharge scheme is proposed for avoiding reversion loss and relaxing the timing restrictions imposed on input clocks. Comparison results in an 80-nm CMOS process indicate that, with no loading current, the output voltage of the proposed charge pump reaches almost 98% of the ideal boosting level with switching ripple reduced by up to 97%. They also indicate that output voltage deviations due to temperature and process variations are reduced by 24%-98% and 81%-95%, respectively.

This brief presents a pulsewidth modulation buck converter with an adaptive ramp amplitude control. The proposed buck converter can improve the load transient response and the reference tracking speed. A chip was fabricated in a 0.18-μm CMOS technology. Measurement results showed that the overshoot/undershoot at the output during the load transient period was reduced by up to 57% for a 450-mA load current step and that the reference tracking speed was improved by up to 71% for a 1.5-V output voltage change. The measured maximum power conversion efficiency was 92.6% at 3-MHz switching frequency when input and output voltages are 3.3 and 2 V, respectively.