Naeem Maroof

Naeem Maroof


Research Focus & Metrics

Academic Career Length

12Years (2015-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

View All Publications
29 December 2016 in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Verified
Journal Article
Closed access
NMNaeem Maroof
Naeem Maroof
BKBai-Sun Kong
Bai-Sun Kong
We present, in this paper, a new 10T static random access memory cell having single ended decoupled read-bitline (RBL) with a 4T read port for low power operation and leakage reduction. The RBL is precharged at half the cell's supply voltage, and is allowed to charge and discharge according to the stored data bit. An inverter, driven by the complementary data node (QB), connects the RBL to the virtual power rails through a transmission gate during the read operation. RBL increases toward the V DD level for a read-1, and discharges toward the ground level for a read-0. Virtual power rails have the same value of the RBL precharging level during the write and the hold mode, and are connected to true supply levels only during the read operation. Dynamic control of virtual rails substantially reduces the RBL leakage. The proposed 10T cell in a commercial 65 nm technology is 2.47× the size of 6T with β = 2, provides 2.3× read static noise margin, and reduces the read power dissipation by 50% than that of 6T. The value of RBL leakage is reduced by more than 3 orders of magnitude and (I ON/ I OFF) is greatly improved compared with the 6T BL leakage. The overall leakage characteristics of 6T and 10T are similar, and competitive performance is achieved.

1 April 2022 in Circuits, Systems, and Signal Processing
Verified
Journal Article
Closed access
PDF file
DCDr. Parameshwar M C
Dr. Parameshwar M C
NMNaeem Maroof
Naeem Maroof

1 June 2022 in Engineering Research Express
Verified
Journal Article
Closed access
DCDr. Parameshwar M C
Dr. Parameshwar M C
NMNaeem Maroof
Naeem Maroof
Angshuman KhanAngshuman Khan
Angshuman Khan
The complementary metal oxide semiconductor (CMOS) technology is approaching its physical limits due to lithographic issues and diminishing benefits of scaling. The new technologies such as quantum dot cellular automata (QCA), tunneling phase logic (TPL), nonmagnetic logic (NML), single electron tunneling (SET), etc are emerging as an alternative and may supersede the conventional CMOS technologies in the near future. Now days, the design of approximate computing based on QCA technologies has gaining much of recent interest. In this paper, a majority-logic (ML) based area-delay efficient novel approximate full adder (AFA) is presented. The QCA layout of proposed AFA is designed and simulated using QCADesigner tool. Further, the proposed AFA is analyzed and compared against the state-of-the-art approximate adders referred to as ‘reported AFAs’ (RAAs), in terms of error metrics (EMs), area, and time complexity. Also, analyzed its efficacy for error-tolerant applications such as image processing.

18 October 2021 in Journal of Circuits, Systems and Computers
Verified
Journal Article
Closed access
PDF file
NMNaeem Maroof
Naeem Maroof
AAAli Y. Al-Zahrani
Ali Y. Al-Zahrani

21 December 2016 in International Journal of Circuit Theory and Applications
Verified
Journal Article
Closed access
PDF file
NMNaeem Maroof
Naeem Maroof
MSMuhammad Sohail
Muhammad Sohail
HSHyunchul Shin
Hyunchul Shin

22 November 2022 in Cluster Computing
Verified
Journal Article
Closed access
PDF file
ABAbdul Basit
Abdul Basit
WTWaqas Tariq Toor
Waqas Tariq Toor
Muhammad SaadiMuhammad Saadi
Muhammad Saadi
NMNaeem Maroof
Naeem Maroof
SKSaqib Ali Khan
Saqib Ali Khan
SASattam Alotaibi
Sattam Alotaibi