Tactile sensors are basically arrays of force sensors that are intended to emulate the skin in applications such as assistive robotics. Local electronics are usually implemented to reduce errors and interference caused by long wires. Realizations based on standard microcontrollers, Programmable Systems on Chip (PSoCs) and Field Programmable Gate Arrays (FPGAs) have been proposed by the authors for the case of piezoresistive tactile sensors. The solution employing FPGAs is especially relevant since their performance is closer to that of Application Specific Integrated Circuits (ASICs) than that of the other devices. This paper presents an implementation of such an idea for a specific sensor. For the purpose of comparison, the circuitry based on the other devices is also made for the same sensor. This paper discusses the implementation issues, provides details regarding the design of the hardware based on the three devices and compares them.

Dexterity in robotic hands is not enough to cover the demands for more flexibility in the manufacturing process. Specifically, processes that involve cooperation or learning from humans, slippage detection and tactile feedback to improve grasp stability when different objects are manipulated, object exploration and classification, quality inspection, welding, etc. The sense of touch is the key to the capabilities of human hands, so tactile sensors must be incorporated into robotic hands to improve them. However, tactile sensing technology is not yet mature enough to be an effective tool. One reason for this limited performance is the need of acquisition and processing of large amounts of data in the short time required to perform a fluent manipulation. Smart tactile sensors can help in this goal if they are able to carry out local acquisition and processing of tactile data and transmit only relevant information through buses that guarantee bounded latency. Field-programmable gate arrays (FPGAs) are devices which are especially suitable for this task due to their ability for parallel processing. This paper presents the realization of electronics for a tactile sensor suite based on FPGAs that implements a direct interface with the raw sensor and serial communication between the fingertips and palm.

The typical layout in a piezoresistive tactile sensor arranges individual sensors to form an array with M rows and N columns. While this layout reduces the wiring involved, it does not allow the values of the sensor resistors to be measured individually due to the appearance of crosstalk caused by the nonidealities of the array reading circuits. In this paper, two reading methods that minimize errors resulting from this phenomenon are assessed by designing an electronic system for array reading, and the results are compared to those obtained using the traditional method, obviating the nonidealities of the reading circuit. The different models were compared by testing the system with an array of discrete resistors. The system was later connected to a tactile sensor with 8 × 7 taxels.

One of the most suitable ways of distributing a resistive sensor array for reading is an array with M rows and N columns. This allows reduced wiring and a certain degree of parallelism in the implementation, although it also introduces crosstalk effects. Several types of circuits can carry out the analogue-digital conversion of this type of sensors. This article focuses on the use of operational amplifiers with capacitive feedback and FPGAs for this task. Specifically, modifications of a previously reported circuit are proposed to reduce the errors due to the non-idealities of the amplifiers and the I/O drivers of the FPGA. Moreover, calibration algorithms are derived from the analysis of the proposed circuitry to reduce the crosstalk error and improve the accuracy. Finally, the performances of the proposals is evaluated experimentally on an array of resistors and for different ranges.

Resistive sensor arrays are formed by a large number of individual sensors which are distributed in different ways. This paper proposes a direct connection between an FPGA and a resistive array distributed in M rows and N columns, without the need of analog-to-digital converters to obtain resistance values in the sensor and where the conditioning circuit is reduced to the use of a capacitor in each of the columns of the matrix. The circuit allows parallel measurements of the N resistors which form each of the rows of the array, eliminating the resistive crosstalk which is typical of these circuits. This is achieved by an addressing technique which does not require external elements to the FPGA. Although the typical resistive crosstalk between resistors which are measured simultaneously is eliminated, other elements that have an impact on the measurement of discharge times appear in the proposed architecture and, therefore, affect the uncertainty in resistance value measurements; these elements need to be studied. Finally, the performance of different calibration techniques is assessed experimentally on a discrete resistor array, obtaining for a new model of calibration, a maximum relative error of 0.066% in a range of resistor values which correspond to a tactile sensor.

Completely eliminating crosstalk effect is the most important challenge when reading a resistive sensor array with M rows and N columns. It may require complex electronics, ranging from a large number of multiplexers and switches to use of M AC voltage sources. More measurements than those considered strictly necessary, M·N, may also be required. Thus, an implementation with multiplexers and switches uses 2·M·N measurements, while this number rises to M·N·L in the one that uses AC voltage sources, where L is the Fourier Transform length required to obtain the sensor readings. This article presents a new circuit and readout method to eliminate crosstalk that simultaneously reduces the total number of multiplexers to M+N and the number of measurements to N·(M+1+(N+1)/2). The unique source of error comes from the non-idealities of the only operational amplifier used. As an added benefit, the new circuit also reduces power consumption of the array by including a single additional resistor.