This paper introduces a digital interface application-specific integrated circuit (ASIC) for a micro-electromechanical systems (MEMS) vibratory gyroscope. The driving circuit of the interface ASIC uses an automatic gain circuit (AGC) module instead of a phase-locked loop to realize a self-excited vibration, which gives the gyroscope system good robustness. In order to realize the co-simulation of the mechanically sensitive structure and interface circuit of the gyroscope, the equivalent electrical model analysis and modeling of the mechanically sensitive structure of the gyro are carried out by Verilog-A. According to the design scheme of the MEMS gyroscope interface circuit, a system-level simulation model including mechanically sensitive structure and measurement and control circuit is established by SIMULINK. A digital-to-analog converter (ADC) is designed for the digital processing and temperature compensation of the angular velocity in the MEMS gyroscope digital circuit system. Using the positive and negative diode temperature characteristics, the function of the on-chip temperature sensor is realized, and the temperature compensation and zero bias correction are carried out simultaneously. The MEMS interface ASIC is designed using a standard 0.18 μM CMOS BCD process. The experimental results show that the signal-to-noise ratio (SNR) of sigma-delta (ΣΔ) ADC is 111.56 dB. The nonlinearity of the MEMS gyroscope system is 0.03% over the full-scale range.

This paper proposes an interface application-specific-integrated-circuit (ASIC) for micro-electromechanical systems (MEMS) vibratory gyroscopes. A closed self-excited drive loop is employed for automatic amplitude stabilization based on peak detection and proportion-integration (PI) controller. A nonlinear multiplier terminating the drive loop is designed for rapid resonance oscillation and linearity improvement. Capacitance variation induced by mechanical motion is detected by a differential charge amplifier in sense mode. After phase demodulation and low-pass filtering an analog signal indicating the input angular velocity is obtained. Non-idealities are further suppressed by on-chip temperature drift calibration. In order for better compatibility with digital circuitry systems, a low passband incremental zoom sigma-delta (ΣΔ) analog-to-digital converter (ADC) is implemented for digital output. Manufactured in a standard 0.35 μm complementary metal-oxide-semiconductor (CMOS) technology, the whole interface occupies an active area of 3.2 mm². Experimental results show a bias instability of 2.2 °/h and a nonlinearity of 0.016% over the full-scale range.

In this paper, a detailed analysis of the influence of phase noise on the micro-electro-mechanical system (MEMS) disk resonator gyroscope (DRG) is presented. Firstly, a new time-varying phase noise model for the gyroscope is established, which explains how the drive loop circuit noise converts into phase noise. Different from previous works, the time-varying phase noise model in this paper is established in mechanical domain, which gain more physical insight into the origin of the phase noise in gyroscope. Furthermore, the impact of phase noise on DRG is derived, which shows how the phase noise affects angular velocity measurement. The analysis shows that, in MEMS DRG, the phase noise, together with other non-ideal factors such as direct excitation of secondary resonator, may cause a low frequency noise in the output of the gyroscope system and affect the bias stability of the gyroscope. Finally, numerical simulations and experiment tests are designed to prove the theories above.

This paper presents a multi-stage noise shaping (MASH) switched-capacitor (SC) sigma-delta (ΣΔ) analog-to-digital converter (ADC) composed of an analog modulator with an on-chip noise cancellation logic and a reconfigurable digital decimator for MEMS digital gyroscope applications. A MASH 2-1-1 structure is employed to guarantee an absolutely stable modulation system. Based on the over-sampling and noise-shaping techniques, the core modulator architecture is a cascade of three single-loop stages containing feedback paths for systematic optimization to avoid deterioration in conversion accuracy caused by capacitor mismatch. A digital noise cancellation logic is also included to eliminate residual quantization errors in the former two stages, and those in the last stage are shaped by a fourth-order modulation. A multi-rate decimator follows the analog modulator to suit variable gyroscope bandwidth. Manufactured in a standard 0.35 μm CMOS technology, the whole chip occupies an area of 3.8 mm². Experimental results show a maximum signal-to-noise ratio (SNR) of 100.2 dB and an overall dynamic range (DR) of 107.6 dB, with a power consumption of 3.2 mW from a 5 V supply. This corresponds to a state-of-the-art figure-of-merit (FoM) of 165.6 dB.

This paper proposes a solution for sensing spatial angular velocity. A high-performance digital interface application specific integrated circuit (ASIC) for triple-axis micro-electromechanical systems (MEMS) vibratory gyroscopes is presented. The technique of time multiplexing is employed for synergetic stable drive control and precise angular velocity measurement in three separate degrees of freedom (DOF). Self-excited digital closed loop drives the proof mass in sensing elements at its inherent resonant frequency for Coriolis force generation during angular rotation. The analog front ends in both drive and sense loops are comprised of low-noise charge-voltage (C/V) converters and multi-channel incremental zoom analog-to-digital converters (ADC), so that capacitance variation between combs induced by mechanical motion is transformed into digital voltage signals. Other circuitry elements, such as loop controlling and accurate demodulation modules, are all implemented in digital logics. Automatic amplitude stabilization is mainly realized by peak detection and proportion-integration (PI) control. Nonlinear digital gain adjustment is designed for rapid establishment of resonance oscillation and linearity improvement. Manufactured in a standard 0.35-μm complementary metal-oxide-semiconductor (CMOS) technology, this design achieves a bias instability of 2.1°/h and a nonlinearity of 0.012% over full-scale range.