A digital closed-loop system design of a microelectromechanical systems (MEMS) disk resonator gyroscope (DRG) is proposed in this paper. Vibration models with non-ideal factors are provided based on the structure characteristics and operation mode of the sensing element. The DRG operates in force balance mode with four control loops. A closed self-excited loop realizes stable vibration amplitude on the basis of peak detection technology and phase control loop. Force-to-rebalance technology is employed for the closed sense loop. A high-frequency carrier loaded on an anchor weakens the effect of parasitic capacitances coupling. The signal detected by the charge amplifier is demodulated and converted into a digital output for subsequent processing. Considering compatibility with digital circuits and output precision demands, a low passband sigma-delta (ΣΔ) analog-to-digital converter (ADC) is implemented with a 111.8dB signal-to-noise ratio (SNR). The analog front-end and digital closed self-excited loop is manufactured with a standard 0.35 µm complementary metal-oxide-semiconductor (CMOS) technology. The experimental results show a bias instability of 2.1 °/h and a nonlinearity of 0.035% over the ± 400° full-scale range.

This paper proposes an interface application-specific-integrated-circuit (ASIC) for micro-electromechanical systems (MEMS) vibratory gyroscopes. A closed self-excited drive loop is employed for automatic amplitude stabilization based on peak detection and proportion-integration (PI) controller. A nonlinear multiplier terminating the drive loop is designed for rapid resonance oscillation and linearity improvement. Capacitance variation induced by mechanical motion is detected by a differential charge amplifier in sense mode. After phase demodulation and low-pass filtering an analog signal indicating the input angular velocity is obtained. Non-idealities are further suppressed by on-chip temperature drift calibration. In order for better compatibility with digital circuitry systems, a low passband incremental zoom sigma-delta (ΣΔ) analog-to-digital converter (ADC) is implemented for digital output. Manufactured in a standard 0.35 μm complementary metal-oxide-semiconductor (CMOS) technology, the whole interface occupies an active area of 3.2 mm². Experimental results show a bias instability of 2.2 °/h and a nonlinearity of 0.016% over the full-scale range.

In this paper, a detailed analysis of the influence of phase noise on the micro-electro-mechanical system (MEMS) disk resonator gyroscope (DRG) is presented. Firstly, a new time-varying phase noise model for the gyroscope is established, which explains how the drive loop circuit noise converts into phase noise. Different from previous works, the time-varying phase noise model in this paper is established in mechanical domain, which gain more physical insight into the origin of the phase noise in gyroscope. Furthermore, the impact of phase noise on DRG is derived, which shows how the phase noise affects angular velocity measurement. The analysis shows that, in MEMS DRG, the phase noise, together with other non-ideal factors such as direct excitation of secondary resonator, may cause a low frequency noise in the output of the gyroscope system and affect the bias stability of the gyroscope. Finally, numerical simulations and experiment tests are designed to prove the theories above.

This paper proposes a low-noise interface application-specific integrated circuit (ASIC) for a microelectromechanical systems (MEMS) disk resonator gyroscope (DRG) which operates in force-to-rebalance (FTR) mode. The ASIC employs an analog closed-loop control scheme which incorporates a self-excited drive loop, a rate loop and a quadrature loop. A ΣΔ modulator and a digital filter are also contained in the design to digitize the analog output besides the control loops. The clocks for the modulator and digital circuits are both generated by the self-clocking circuit, which avoids the requirement of additional quartz crystal. A system-level noise model is established to determine the contribution of each noise source in order to reduce the noise at the output. A noise optimization solution suitable for chip integration is proposed based on system-level analysis, which can effectively avoid the effects of the 1/f noise of the PI amplifier and the white noise of the feedback element. A performance of 0.0075°/√h angle random walk (ARW) and 0.038°/h bias instability (BI) is achieved using the proposed noise optimization method. The ASIC is fabricated in a 0.35 μm process with a die area of 4.4 mm × 4.5 mm and power consumption of 50 mW.

This paper proposes a novel design method of the mode-matched disk resonator gyroscope (DRG) realized by the monolithic integrated interface circuit. The mode-mismatched dynamics model of DRG is simplified by introducing the analysis method of ”slow” dynamics, and the effect of mode-mismatching is quantified and the automatic mode-matched interface circuit is designed based on the analysis of simplified model. The force-rebalance loop is designed based on self-clock circuit, which releases the chip from the dependence on external clocks, avoids the design of multipliers, ADCs and DACs, and improves the integration of the chip. The highly integrated automatic mode-matching loop is realized by the designing of quadrature loop and stiffness tuning loop on the basics of mode-matching theory. The design method is applied to develop a monolithic integrated interface chip of DRG with the area of 4.2mm×4.3mm and the power consumption of 90mw. The DRG integrated circuit achieves the bias instability (BI) of 0.38°/h and the angle random walk (ARW) of 0.0354°/√h within a full scale of ±300°/s, which provides a highly integrated circuit design scheme for DRG extensive application.