Time derivative estimation of signals plays a very important role in several fields, such as signal processing and control engineering, just to name a few of them. For that purpose, a non-asymptotic algebraic procedure for the approximate estimation of the system states is used in this work. The method is based on results from differential algebra and furnishes some general formulae for the time derivatives of a measurable signal in which two algebraic derivative estimators run simultaneously, but in an overlapping fashion. The algebraic derivative algorithm presented in this paper is computed online and in real-time, offering high robustness properties with regard to corrupting noises, versatility and ease of implementation. Besides, in this work, we introduce a novel architecture to accelerate this algebraic derivative estimator using reconfigurable logic. The core of the algorithm is implemented in an FPGA, improving the speed of the system and achieving real-time performance. Finally, this work proposes a low-cost platform for the integration of hardware in the loop in MATLAB.

High-Level Synthesis (HLS) tools provide facilities for the development of specialized hardware accelerators (HWacc). However, the verification stage is still the longest phase in the development life-cycle. Unlike in the software industry, HLS tools lack testing frameworks that could cover the whole design flow, especially the on-board verification stage of the generated RTL. This work introduces a framework for on-board verification of HLS-based modules by using reconfigurable systems and Docker containers with the aim to automate the verification process and preserve a clean testing environment, making the testbed reusable across different stages of the design flow. Moreover, our solution features a mechanism to check timing requirements of the HWacc. We have applied our solution to the C-kernels of the CHStone Benchmark on a Zedboard, in which the on-board verification process has been accelerated up to four times.

High-Level Synthesis (HLS) tools help engineers to deal with the complexity of building heterogeneous embedded systems that make it use of reconfigurable technology. Also, HLS opens up a way for introducing, into the development flow of custom hardware components, techniques well known in the software industry such as Test-Driven Development (TDD). However, the support provided by HLS tools for verification activities is limited, and it is usually focused on the initial steps of the design process. In this paper, a hardware testing framework is introduced as an enabler for effortless on-board verification of components by applying the Unit Testing Paradigm and, hence, realizing TDD on reconfigurable hardware. The proposed solution comprises a hardware/software introspection infrastructure to verify modules of a system at different stages, spawning multiple abstraction levels without extra effort nor redesigning the component. Our solution has been implemented for the Xilinx ZynQ FPGA-SoC architecture and applied to the verification of C-kernels within the CHStone Benchmark. Effortless integration into the Xilinx Vivado design flow and tools is supported by a set of automatic generation scripts developed for this end. Experimental results show a considerable speedup of the verification time and unveils inaccuracies concerning the co-simulation estimation obtained by Xilinx tools when compared with the on-board latency measured by our framework.

As the term smart begins to move away from inflationary usage, mostly related to communication capabilities, and towards a more effective dimension, there is room for research into the systematic process of transforming the things that were not originally designed to be smart. Such a process is referred to as smartification, which evokes the digital refinement of an existing product by embedding digital technologies and smart services. The state of the art shows only a few articles that investigate such methodological approaches to provide smartness on several application domains (e.g., home appliances, buildings, cities), while the smart university domain has not been deeply faced up yet. Based on the hypothesis that a methodology synthesizes a set of suitable procedures oriented to simplify the process of measuring the degree of smartification, we propose in this work a methodology that uses technological and academic criteria for designing a tool to measure the smartification of universities. The main conclusions of this work are the following: (1) The review of the current state of the art related to smart universities and smartification reveals the need for a new vision for a more adequate and accurate assessment of the degree of smartness of universities; (2) A formal method based on Multiple-Attribute Decision Making and case study research aimed at assessing the degree of smartification within the scope of smart universities; (3) A demonstration of the feasibility and application of our method to quantify the smartification degree of the School of Computer Science (ESI) at the University of Castilla-La Mancha under the project Smart ESI; and (4) A valuable method that allows equal comparison between smart universities through a set of standardized indicators, which offers the opportunity to analyze in depth the strength and weakness, and potential achievements of any smart initiatives. To the authors’ knowledge, this is the first approach aimed at assessing the extent of the smartification process in smart universities through a formal method. The outcome of this research can benefit different stakeholders: university community, researchers, and, ultimately, the digital transformation of society.

Real-time video image processing requires video compression techniques. Efficient Motion Estimation (ME) and Motion Compensation (MC) algorithms and their successful hardware implementation are the key to video compression. Work on developing and implementing efficient ME and MC algorithms for multi-camera systems is ongoing. The low power consumption yet high speed of Heterogeneous Reconfigurable Devices such as Field Programmable Gate Arrays (FPGA) can be suitable for implementation of real-time optic flow computation using multi-camera systems. This paper focuses on a search into the current state-of-the-art for multi-camera motion tracking. It has been found the tracking systems mainly focused on people and vehicle tracking in both indoor and outdoor conditions, tracking under occlusion, tracking for surveillance, single and multi-view tracking, etc. The review search also found use of multi-camera tracking in the medical sector, such as multi-camera tracking systems for respiratory motion tracking. Research on this field has not been explored much and this holds possibilities for further work.

This document presents a persistence management model for reconfigurable SoC. This model provides an efficient mechanism for persistence to preserve data information of hardware components that are swapped out of dynamically reconfigurable areas, in order to allow the reinsertion of these components and to restart the execution path from the same point where they were interrupted when reinserted. This mechanism allows state management of components instantiated not only in reconfigurable areas, but also for those instantiated in static areas, that are feasible to be stopped and replaced for new versions instantiated in hardware or implemented in software migrating their state to the new ones.