Medical images and videos are utilized to discover, diagnose and treat diseases. Managing, storing, and retrieving stored images effectively are considered important topics. The rapid growth of multimedia data, including medical images and videos, has caused a swift rise in data transmission volume and repository size. Multimedia data contains useful information; however, it consumes an enormous storage space. Therefore, high processing time for that sheer volume of data will be required. Image and video applications demand for reduction in computational cost (processing time) when extracting features. This paper introduces a novel method to compute transform coefficients (features) from images or video frames. These features are used to represent the local visual content of images and video frames. We compared the proposed method with the traditional approach of feature extraction using a standard image technique. Furthermore, the proposed method is employed for shot boundary detection (SBD) applications to detect transitions in video frames. The standard TRECVID 2005, 2006, and 2007 video datasets are used to evaluate the performance of the SBD applications. The achieved results show that the proposed algorithm significantly reduces the computational cost in comparison to the traditional method.

Achieving reliable operation under the influence of deep-submicrometer noise sources including crosstalk noise at low voltage operation is a major challenge for network on chip links. In this paper, we propose a coding scheme that simultaneously addresses crosstalk effects on signal delay and detects up to seven random errors through wire duplication and simple parity checks calculated over the rows and columns of the two-dimensional data. This high error detection capability enables the reduction of operating voltage on the wire leading to energy saving. The results show that the proposed scheme reduces the energy consumption up to 53% as compared to other schemes at iso-reliability performance despite the increase in the overhead number of wires. In addition, it has small penalty on the network performance, represented by the average latency and comparable codec area overhead to other schemes.

Deep submicron technologies continue to develop according to Moore’s law allowing hundreds of processing elements and memory modules to be integrated on a single chip forming multi/many-processor systems-on-chip (MPSoCs). Network on chip (NoC) arose as an interconnection for this large number of processing modules. However, the aggressive scaling of transistors makes NoC more vulnerable to both permanent and transient faults. Permanent faults persistently affect the circuit functionality from the time of their occurrence. The router represents the heart of the NoC. Thus, this research focuses on tolerating permanent faults in the router’s input buffer component, particularly the virtual channel state fields. These fields track packets from the moment they enter the input component until they leave to the next router. The hardware redundancy approach is used to tolerate the faults in these fields due to their crucial role in managing the router operation. A built-in self-test logic is integrated into the input port to periodically detect permanent faults without interrupting router operation. These approaches make the NoC router more reliable than the unprotected NoC router with a maximum of 17% and 16% area and power overheads, respectively. In addition, the hardware redundancy approach preserves the network performance in the presence of a single fault by avoiding the virtual channel closure.

The presence of different noise sources and continuous increase in crosstalk in the deep submicrometer technology raised concerns for on-chip communication reliability, leading to the incorporation of crosstalk avoidance techniques in error control coding schemes. This brief proposes joint crosstalk avoidance with adaptive error control scheme to reduce the power consumption by providing appropriate communication resiliency based on runtime noise level. By switching between shielding and duplication as the crosstalk avoidance technique and between hybrid automatic repeat request and forward error correction as the error control policies, three modes of error resiliencies are provided. The results show that, in reduced mode, the scheme achieves up to 25.3% power savings at 3-mm wire length as compared to the original nonadaptive scheme at the cost of only 3.4% power overhead in high protection mode.

Tchebichef polynomials (TPs) play a crucial role in various fields of mathematics and applied sciences, including numerical analysis, image and signal processing, and computer vision. This is due to the unique properties of the TPs and their remarkable performance. Nowadays, the demand for high-quality images (2D signals) is increasing and is expected to continue growing. The processing of these signals requires the generation of accurate and fast polynomials. The existing algorithms generate the TPs sequentially, and this is considered as computationally costly for high-order and larger-sized polynomials. To this end, we present a new efficient solution to overcome the limitation of sequential algorithms. The presented algorithm uses the parallel processing paradigm to leverage the computation cost. This is performed by utilizing the multicore and multithreading features of a CPU. The implementation of multithreaded algorithms for computing TP coefficients segments the computations into sub-tasks. These sub-tasks are executed concurrently on several threads across the available cores. The performance of the multithreaded algorithm is evaluated on various TP sizes, which demonstrates a significant improvement in computation time. Furthermore, a selection for the appropriate number of threads for the proposed algorithm is introduced. The results reveal that the proposed algorithm enhances the computation performance to provide a quick, steady, and accurate computation of the TP coefficients, making it a practical solution for different applications.

Orthogonal polynomials and their moments serve as pivotal elements across various fields. Discrete Krawtchouk polynomials (DKraPs) are considered a versatile family of orthogonal polynomials and are widely used in different fields such as probability theory, signal processing, digital communications, and image processing. Various recurrence algorithms have been proposed so far to address the challenge of numerical instability for large values of orders and signal sizes. The computation of DKraP coefficients was typically computed using sequential algorithms, which are computationally extensive for large order values and polynomial sizes. To this end, this paper introduces a computationally efficient solution that utilizes the parallel processing capabilities of modern central processing units (CPUs), namely the availability of multiple cores and multithreading. The proposed multi-threaded implementations for computing DKraP coefficients divide the computations into multiple independent tasks, which are executed concurrently by different threads distributed among the independent cores. This multi-threaded approach has been evaluated across a range of DKraP sizes and various values of polynomial parameters. The results show that the proposed method achieves a significant reduction in computation time. In addition, the proposed method has the added benefit of applying to larger polynomial sizes and a wider range of Krawtchouk polynomial parameters. Furthermore, an accurate and appropriate selection scheme of the recurrence algorithm is introduced. The proposed approach introduced in this paper makes the DKraP coefficient computation an attractive solution for a variety of applications.