Today, the introduction of wide band gap (WBG) semiconductors in power electronics has become mandatory to improve the energy efficiency of devices and modules and to reduce the overall electric power consumption in the world. Due to its excellent properties, gallium nitride (GaN) and related alloys (e.g., Al_xGa_1−xN) are promising semiconductors for the next generation of high-power and high-frequency devices. However, there are still several technological concerns hindering the complete exploitation of these materials. As an example, high electron mobility transistors (HEMTs) based on AlGaN/GaN heterostructures are inherently normally-on devices. However, normally-off operation is often desired in many power electronics applications. This review paper will give a brief overview on some scientific and technological aspects related to the current normally-off GaN HEMTs technology. A special focus will be put on the p-GaN gate and on the recessed gate hybrid metal insulator semiconductor high electron mobility transistor (MISHEMT), discussing the role of the metal on the p-GaN gate and of the insulator in the recessed MISHEMT region. Finally, the advantages and disadvantages in the processing and performances of the most common technological solutions for normally-off GaN transistors will be summarized.

This paper gives an overview on some state-of-the-art characterization methods of SiO₂/4H-SiC interfaces in metal oxide semiconductor field effect transistors (MOSFETs). In particular, the work compares the benefits and drawbacks of different techniques to assess the physical parameters describing the electronic properties and the current transport at the SiO₂/SiC interfaces (interface states, channel mobility, trapping phenomena, etc.). First, the most common electrical characterization techniques of SiO₂/SiC interfaces are presented (e.g., capacitance- and current-voltage techniques, transient capacitance, and current measurements). Then, examples of electrical characterizations at the nanoscale (by scanning probe microscopy techniques) are given, to get insights on the homogeneity of the SiO₂/SiC interface and the local interfacial doping effects occurring upon annealing. The trapping effects occurring in SiO₂/4H-SiC MOS systems are elucidated using advanced capacitance and current measurements as a function of time. In particular, these measurements give information on the density (~10¹¹ cm⁻²) of near interface oxide traps (NIOTs) present inside the SiO₂ layer and their position with respect to the interface with SiC (at about 1–2 nm). Finally, it will be shown that a comparison of the electrical data with advanced structural and chemical characterization methods makes it possible to ascribe the NIOTs to the presence of a sub-stoichiometric SiO_x layer at the interface.

A combined powder X-ray lattice parameter and ceramic impedance spectroscopy study is presented on materials within the CaO–CuO–TiO₂ ternary phase diagram. Several compositions containing CaCu₃Ti₄O₁₂ (CCTO) and small amounts of secondary phases such as TiO₂, CaTiO₃ and CuO are analysed and two different defect mechanisms are identified as the cause of the non-stoichiometry in CCTO. The first mechanism involves a variation in the Cu content, which explains the large differences in the intrinsic bulk and extrinsic grain boundary (GB) resistance, and the formation of the ceramic internal barrier layer capacitor (IBLC) structure. The second mechanism is associated with Ca–Cu anti-site disorder causing an unusually high intrinsic bulk permittivity above that predicted from Clausius–Mossotti calculations.