The application of flexible electronics in the field of communication has made the transition from rigid physical form to flexible physical form. Flexible electrode technology is the key to the wide application of flexible electronics. However, flexible electrodes will break when large deformation occurs, failing flexible electronics. It restricts the further development of flexible electronic technology. Flexible stretchable electrodes are a hot research topic to solve the problem that flexible electrodes cannot withstand large deformation. Flexible stretchable electrode materials have excellent electrical conductivity, while retaining excellent mechanical properties in case of large deformation. This paper summarizes the research results of flexible stretchable electrodes from three aspects: material, process, and structure, as well as the prospects for future development.

This paper proposes a SAR ADC whose readout speed is improved by 33%, through applying a digital error correction (DEC) method, compared to an alternative without using the DEC technique. The proposed addition-only DEC alleviates the ADC’s incomplete settling errors, hence improving conversion rate while maintaining accuracy. It is based on a binary bridged SAR architecture with 4 redundant capacitors and conversion cycles, which ensure the ADC’s linearity of 10 bit within a 5 bit accuracy’s settling time. The proposed SAR keeps the same straightforward timing diagram as that in a conventional SAR ADC, incurring no offset to the ADC. Measurement results of 15 columns of SAR ADCs, sampling at 5 MS/s on the same CMOS image sensor (CIS) chip, show integral nonlinearity (INL) around 3 LSB (1LSB = 1mV), when sampling at 5 MHz, after a proposed swift digital background calibration that incurs no additional hardware complexity. The CIS array read out by the proposed column-level SAR ADCs is measured reasonable photoelectron transfer characteristics.

This paper proposes employing each of the classical 4 transistor (4T) pinned photodiode (PPD) CMOS image sensor (CIS) pixels, for both imaging and temperature measurement, intended for compensating the CISs’ dark current and dark signal non-uniformity (DSNU). The proposed temperature sensors rely on the thermal behavior of MOSFETs working in subthreshold region, when biased with ratiometric currents sequentially. Without incurring any additional hardware or penalty to the CIS, they are measured to have thermal curvature errors less than ±0.3 ∘C and 3 σ process variations within ±1.3 ∘C, from 108 sensors on 4 chips, over a temperature range from -20 ∘C to 80 ∘C. Each of them consumes 576 nJ/conversion at a conversion rate of 62 samples/s, when quantized by 1st-order 14 bit delta-sigma ADCs and fabricated using 0.18 μm CIS technology. Experimental results show that they facilitate digital compensation for average dark current and DSNU by 78 % and 20 %, respectively.

This paper proposes various types of on-chip smart temperature sensors, intended for thermal compensation of dark current in CMOS image sensors (CIS). It proposes 4 different architectures of metal oxide semiconductor (MOS) based and bipolar junction transistor (BJT) based temperature sensors, inside and outside the CIS array. Both of the MOS based temperature sensors make use of the thermal dependence of MOS transistors working in subthreshold region with ratiometric currents and are quantized by 14-bit 1st order incremental delta-sigma ADCs. Fabricated using 0.18 μm CIS technology and measured on 4 chips, the proposed temperature sensors are compared, on their resolution and process variability, as well as on their effects on the neighboring image pixels implemented on the same chip. Experimental results show the MOS based temperature sensors inside and outside the array consume a power of 36 μW and 40 μW, respectively, both achieving 3 sigma (σ) inaccuracy less than ±0.75°C on 4 different chips, over a temperature range from.20°C to 80°C, at a conversion time of 16 ms. The temperature sensors facilitate digital thermal compensation of dark current in the CIS array, by at least 80 %, in experiments.

This review paper categorizes the state-of-the-art MOS (metal oxide semiconductor)-based temperature sensors according to their thermal sensing principles, including: type I, the logic, saturation and linear MOS-based temperature sensors; type II, the subthreshold MOS-based temperature sensors; and type III, the gate leakage-based temperature sensors. It also discusses in detail the design considerations and challenges of MOS-based temperature sensors, in terms of area, energy efficiency, supply voltage, inaccuracy, noise, as well as process and power supply variations. Based on the aforementioned discussions, the paper concludes that the future MOS-based temperature sensors will mostly likely be based on subthreshold MOS operation, with better trade-offs between area, energy efficiency and accuracy, and with reduced power supply sensitivity and level, as well as a lower-cost, fewer-point calibration method.