A CMOS image sensor (CIS) that can perform on-chip binary convolution is presented. The CIS can greatly reduce memory usage and computational complexity by directly generating a feature map for a binary neural network. The pixel readout of the CIS is performed in the column-parallel fashion using incremental delta-sigma analog-to-digital converters (ADCs). The CIS operates in two different modes: convolution and normal modes. When the column ADC is working in the convolution mode, it works as a first-order delta-sigma ADC and generates convolved images using a binary kernel. In the normal operation mode, the ADC is switched to a second-order delta-sigma ADC with little hardware modification and used to capture high-quality images. To demonstrate the CIS architecture, a 192 × 128-pixel CIS, which occupies an active die area of 14.44 mm ² , is fabricated in a 0.18 μm standard CMOS process. The performance of the CIS is evaluated through measurements and network simulations. In the normal operation mode, the CIS achieves a read noise of 14.79 e ^- _rms and a full-well capacity of 6,420 e ^- with a resulting dynamic range of 53 dB. The power consumptions of the CIS are 49.2 and 52.5 mW during the normal and convolution modes, respectively.

This paper presents a high full well capacity (FWC) CMOS image sensor (CIS) for space applications. The proposed pixel design effectively increases the FWC without inducing overflow of photo-generated charge in a limited pixel area. An MOS capacitor is integrated in a pixel and accumulated charges in a photodiode are transferred to the in-pixel capacitor multiple times depending on the maximum incident light intensity. In addition, the modulation transfer function (MTF) and radiation damage effect on the pixel, which are especially important for space applications, are studied and analyzed through fabrication of the CIS. The CIS was fabricated using a 0.11 μm 1-poly 4-metal CIS process to demonstrate the proposed techniques and pixel design. A measured FWC of 103,448 electrons and MTF improvement of 300% are achieved with 6.5 μm pixel pitch.

This paper presents a new analog-to-digital conversion scheme for a 2nd-order ΣΔ incremental analog to digital converter (ADC) that can be employed in a compressive sensing (CS) based CMOS image sensor (CIS) as a column-parallel ADC. The conversion scheme removes image distortion from a reconstructed image by making the ADC output codes represent an average of the ADC inputs. In addition, a new multiplexing scheme implementing a compressive sensing matrix helps to reduce hardware complexity and control compression ratio without hardware modifications. A 160 × 160 pixel CS based CIS fabricated in 0.11 μm CIS process successfully demonstrates the proposed schemes.

A CMOS image sensor (CIS) that performs compressive sensing (CS) image encoding without compromising the operating speed and hardware complexity is presented in this article. The conversion rate and the frame rate of the sensor are increased by using a high-order sigma-delta (ΣΔ) analog-to-digital converter (ADC) to obtain linear measurements of selected pixel values for CS encoding. Image distortion caused by the nonconstant weight function of high-order ΣΔ ADCs is eliminated by using the proposed sampling technique. The sampling technique makes the effective weights of the inputs to the ADC equal by applying a solution for the set partition problem. In addition, unlike the existing block-based CS encoding scheme that requires complicated analog multiplexers, the proposed column-based CS encoding scheme can be implemented in a hardware-efficient column-parallel fashion, as in conventional CISs. The CIS is fabricated in a 0.11-μm 1P4M CIS process, and the sampling technique and encoding scheme are successfully demonstrated. It achieves a readout noise of 2.63 e ^- _rms and a dynamic range of 67.96 dB with a power consumption of 56.38 mW. The resulting figure of merit is 0.375 e ^- ·nJ, which is the lowest among those of recently reported state-of-the-art CS-CISs.

This paper presents an incremental delta sigma analog to digital converter (ADC) using an extended counting technique for CMOS image sensors. A modified extended counting method is proposed to reduce the over sampling ratio (OSR) and consequently increase conversion speed without increasing the hardware complexity. To further reduce the chip size and power consumption, a self-biased amplifier is shared between the adjacent stages of the delta-sigma modulator. The proposed ADC is fabricated in a 0.18-㎛ CMOS image sensor process and occupies 0.0026 ㎟. It achieves 65 ㏈ of signal noise and distortion ratio (SNDR) for a signal bandwidth of 156.25 ㎑ with a 20 ㎒ operating clock and consumes 45 μW from a 1.8 V power supply. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.49 / −0.22 and +0.61 / −0.64 LSB (least significant byte), respectively.