This paper presents an optimized 3-coil inductive wireless power transfer (WPT) system at 13.56 MHz and 40.68 MHz to show and compare the specific absorption rate (SAR) effects on human tissue. This work also substantiates the effects of perfect alignment, lateral and/or angular misalignments on the power transfer efficiency (PTE) of the proposed WPT system. Additionally, the impacts of different tissue composition, input power and coil shape on the SAR are analyzed. The distance between the external and implantable coils is 10 mm. The results have been verified through simulations and measurements. The simulated results show that the SAR of the system at 40.68 MHz had crossed the limit designated by the Federal Communications Commission and hence, it is unsafe and causes tissue damage. Measurement results of the system in air medium show that the optimized printed circuit board coils at 13.56 MHz achieved a PTE of 41.7% whereas PTE waned to 18.2% and 15.4% at 10 mm of lateral misalignment and 60° of angular misalignment respectively. The PTE of a combination of 10 mm lateral misalignment and 60° angular misalignment is 21%. To analyze in a real-environment, a boneless pork sample with 10 mm of thickness is placed as a medium between the external and implantable coils. At perfect alignment, the PTE through pork sample is 30.8%. A RF power generator operating at 13.56 MHz provides 1 W input power to the external coil and the power delivered to load through the air and tissue mediums are 347 mW and 266 mW respectively.

Inductive power links are most viable for the long-term powering of cardiac pacemakers. Designing an inductive power link without surpassing the specific absorption rate (SAR) for modern leadless cardiac pacemakers (LCPs) remains a challenging task because of its size and implantation depth. The inductive power link employed in the conventional works is either designed at a high frequency or based on the size, shape, weight, and implantation depth of conventional cardiac pacemakers. Here, a 3-coil inductive power transfer link with a circular transmitter coil and solenoidal receiver coil is designed at 13.56 MHz to provide uninterrupted power to the modern LCPs. Considering the food and drug administration approved term for implant size of modern LCP, the receiver coil is designed with 6 mm diameter and 6.5 mm length. The performance of the link has been verified through simulations and measurements under perfect alignment, lateral and/or angular misalignments, and distance variation between the coils. At a 50 mm horizontal distance between transmitter and receiver coils, the transmission coefficient is −30.9 dB. The maximum simulated average SAR at heterogeneous phantom is 0.30 W/kg, which is lower than the limit set by the Federal Communications Commission for radiation threshold exposure. Experiments conducted on pork’s heart verified the reliability of the simulated results. At a 50 mm distance between the coils, the measured transmission coefficient is −34 dB, and at an input power of 1 W, the power delivered to the load is 0.7 mW.

Modern processors have improved performance but still face challenges such as power consumption, storage limitations, and the need for faster processing. The 16-bit Digital Signal Processors (DSPs) accelerate DSP applications by significantly enhancing speed and performance for tasks including audio processing, telecommunications, image and video processing, wireless communication, and consumer electronics. This paper presents a novel technique for accelerating DSP applications on a 16-bit processor by combining two methods: Block Random Access Memory (BRAM) and Distributed Arithmetic (DA). Integrating BRAM as a replacement for conventional RAM minimizes timing and critical route delays, improving processor efficiency and performance. Furthermore, the Distributed Arithmetic approach enhances performance and efficiency by utilizing precomputed lookup tables to expedite multiplication operations within the Arithmetic and Logic Unit (ALU). We use the Xilinx Vivado tool, a robust development environment for FPGA-based systems, for the design process and execute the hardware implementation using the Genesys2 Kintex board. The proposed work produces improved efficiency with a cycle per instruction of 2, where the delay is 2.009 ns, the critical path delay is 8.182 ns, and the power consumption is 4 mW.