Broadband GaN HEMT power amplifier with shunt feedback and push-pull technique is presented. Shunt-feedback and push-pull realization provide the robust broad bandwidth covering VHF and low-frequency UHF bands. The benefit due to the feedback presented in the form of shunt-shunt network on power amplifier module provides the linear and broadband frequency amplification. The push-pull topology provides enhanced efficiency and high power generation along with the cancellation of the second-order distortions and thus helps to compensate for the efficiency degradation from the feedback. These techniques are realized with the help of in-house designed GaN HEMT transistor, which provides high power, good efficiency, and high reliability (bandgap). The prototype was realized in 0.25μm GaN HEMT, operates from 30 to 520 MHz, and dissipates 650mA of quiescent current from 28V supply. The power amplifier delivered a saturated output power of > 43 dBm and < 1 dB gain flatness with > 40% PAE at 20W output power. The linearity of the amplifier was characterized by the two-tone injection test. The measurement result shows that the 3rd-order intermodulation distortion tones are below -35 dBc at 35 dBm output power.

This article presents the crystal-less CMOS frequency reference circuit that is suitable for connectivity applications with a relaxed frequency drift requirement. The presented architecture exploits the open-loop LC oscillator while ensuring constant bias condition, temperature-insensitive operation with an on-chip temperature sensor and digital control logics comprising an adaptive frequency calibration circuit and a non-volatile memory (NVM) performing frequency setup and temperature compensation of the LC oscillator. From 4.12-GHz LC oscillator output frequency, the divide-by-2 circuit followed by the multi modulus divider with 8-256 divide ratio provides 8.05-257.6-MHz output frequencies. The prototype circuit is measured at 27.12-MHz output frequency with ten devices under test and achieves ± 50 ppm frequency accuracy (drift) over temperature variation from -40 °C to 80 °C. The measured period jitter in root-mean-squared is 1.32 psrms. Fabricated in the low-cost 0.18 μm CMOS technology, a temperature compensated frequency reference circuit occupies 0.69 mm² and dissipates 15 mA from a 1.8-V supply voltage.

Inductive power links are most viable for the long-term powering of cardiac pacemakers. Designing an inductive power link without surpassing the specific absorption rate (SAR) for modern leadless cardiac pacemakers (LCPs) remains a challenging task because of its size and implantation depth. The inductive power link employed in the conventional works is either designed at a high frequency or based on the size, shape, weight, and implantation depth of conventional cardiac pacemakers. Here, a 3-coil inductive power transfer link with a circular transmitter coil and solenoidal receiver coil is designed at 13.56 MHz to provide uninterrupted power to the modern LCPs. Considering the food and drug administration approved term for implant size of modern LCP, the receiver coil is designed with 6 mm diameter and 6.5 mm length. The performance of the link has been verified through simulations and measurements under perfect alignment, lateral and/or angular misalignments, and distance variation between the coils. At a 50 mm horizontal distance between transmitter and receiver coils, the transmission coefficient is −30.9 dB. The maximum simulated average SAR at heterogeneous phantom is 0.30 W/kg, which is lower than the limit set by the Federal Communications Commission for radiation threshold exposure. Experiments conducted on pork’s heart verified the reliability of the simulated results. At a 50 mm distance between the coils, the measured transmission coefficient is −34 dB, and at an input power of 1 W, the power delivered to the load is 0.7 mW.

A time-based matrix multiply-and-accumulate (MAC) operation for a neural computing system is described. A simple and compact time-based matrix MAC structure is proposed that can perform multiplication and accumulation simultaneously in a single multiplier structure, and the hardware complexity is not affected by the matrix input size. To enhance the linearity of the weight factor, an offset-free pulse-width modulator is introduced. The proposed MAC architecture operates at a low supply voltage of 0.5 V while it consumes MAC energy of 0.38 pJ with a 32 nm low-power (LP) predictive technology model (PTM) CMOS process. In addition, the near-subthreshold operation can remove the level shifter to interface between the MAC operator and digital circuits such as static random-access-memory (SRAM) because both can utilize the same level of the supply voltage. The proposed MAC is based on a digital intensive pulse-width modulation, and thus it can further improve its performance and area with more advanced technologies.

An efficient class-G stage based on a class-D power amplifier (PA) for switching RF PA applications is described. Class-G operation is achieved by introducing one additional transistor in a cascoded class-D PA, that can reduce area as well as enhance efficiency when compared to prior class-G designs. In addition, a multi-level switching operation is proposed which provides stacked class-G PA operation without using any additional switches. The stacked PA can avoid the requirement for an extra supply voltage for class-G operation. The efficiency and losses in the proposed design, as well as conventional designs, at various output power levels are analyzed by utilizing these in a 5-bit switched-capacitor PA (SCPA). A stacked class-G design with single supply voltage is also compared to an unstacked dual-supply class-G design. While the proposed approach has been explored in a SCPA, the approach can be applied to any switching RF PA architecture that employs a class-D PA.

One important design aspect of a high-voltage gate driver integrated circuit (HVIC) is safety because the failure operation such as latch-on failure may cause severe damage to the system and may pose physical harm to the user. In the HVIC, a noise on the high-side supply voltage was considered as the main source of failure operation, however, a low-side supply voltage noise also can cause latch-on failure to the high-side circuitry. In this brief, the failure caused by the high-side as well as low-side supply voltage noise is analyzed, and a supply voltage noise immunity enhancement design for HVIC is described. The HVIC has been implemented in a 1.2 μm 600 V BCDMOS process. The proposed design shows a latch-on free operation from the various slope of the supply voltage drops while the conventional design shows shoot-through failure by latch-on failure. The approach is well suited for the harsh supply voltage environment such as the automotive application.