This paper proposes a reconfigurable system on chip (SoC) for smart power applications. The system is composed of an ultra-low-power microcontroller for standard software programmability, coupled to an embedded-FPGA (eFPGA) to perform control-driven applications and lightweight digital signal processing, at lower power consumption and higher responsiveness than with processor-based execution. To the best of our knowledge, this is the first heterogeneous reconfigurable SoC targeting smart power applications. The SoC targets BCD technologies integrating bipolar, CMOS, and DMOS devices, typically featuring a small number of metal layers when compared with the traditional CMOS technologies. The added value of the proposed system is that the digital system is fully synthesizable since the eFPGA is based on a soft-core approach. This paper presents the results of integrating an eFPGA with a computational capability of ≃1k equivalent gates in STMicroelectronics 90-nm BCD technology featuring five metal layers and high-k transistors. We benchmarked our architecture on a wide range of applications relevant to the smart power domain. eFPGA integration in SoCs introduces a 20%endash27% area overhead but has a straightforward benefit in terms of energy consumption, which proves reduction from about 10x to 800x. In terms of latency, the eFPGA implementation allows a gain from 8x to 145x comparing the pure cycles count.

Data-intensive processing in embedded systems is receiving much attention in multimedia computing and high-speed telecommunications. The memory bandwidth problem of traditional von Neumann architectures, however, is impairing processor efficiency. On the other hand, ASIC designs suffer from skyrocketing manufacturing costs and long development cycles. This results in an increasing need for postfabrication programmability at both software and hardware levels. FPGAs provide maximum flexibility with their fine-grained architecture but bring severe overhead in timing, area, and power consumption. Wordor subword-oriented runtime reconfigurable architectures offer highly parallel, scalable solutions combining hardware performance with software flexibility.1 Their coarser granularity reduces area, delay, power consumption, and reconfiguration time, but they introduce trade-offs in processing-element design.

This paper analyzes the properties of a class of congestion-free multistage switching networks (MSSNs) are butterfly-based and suitable for embedded programmable devices, which require sustaining static multicast connectivity. These MSSNs are fully synthesizable and enable the design of programmable IPs with typical size in the order of 1 KLUT, coupling flexibility with fast turn-around time. The non-blocking property for static connection of this class of MSSN is discussed. Our analysis shows pros and cons of adopting radix-2 or radix-4 MSSN structures, as well as the impact of bypass-paths to make the network fully hierarchical and locality-aware thanks also to a dedicated programming strategy. Implementation experiments carried out on STM CMOS 65 nm technology show the availability of various area-speed trade-offs, resulting in a range of ≃2× in frequency and a range of ≃ $4\times$ in area. Depending on the specific application-field, an optimal interconnect definition is thus achieved without compromising the routability properties. In this respect, the paper proposes a simplified application-driven model for evaluation of the best MSSN, including bypass-adoption and radix selection.