Most modern 16-bit and 32-bit embedded processors contain cache memories to further increase instruction throughput of the device. Embedded processors that contain cache memories open an opportunity for the low-power research community to model the impact of cache energy consumption and throughput gains. For optimal cache memory configuration mathematical models have been proposed in the past. Most of these models are complex enough to be adapted for modern applications like run-time cache reconfiguration. This paper improves and validates previously proposed energy and throughput models for a data cache, which could be used for overhead analysis for various cache types with relatively small amount of inputs. These models analyze the energy and throughput of a data cache on an application basis, thus providing the hardware and software designer with the feedback vital to tune the cache or application for a given energy budget. The models are suitable for use at design time in the cache optimization process for embedded processors considering time and energy overhead or could be employed at runtime for reconfigurable architectures.

Multicore architectures offer an amount of parallelism that is often underutilized, as a result these underutilized resources become a liability instead of advantage. Inefficient resource sharing on the chip can have a negative impact on the performance of an application and may result in greater energy consumption. A large body of research now focuses on reconfigurable multicore architectures in order to support algorithms to find optimal solutions for improved energy and throughput balance. An ideal system would be able to optimize such reconfigurable systems to a level that optimum resources are allocated to a particular workload and all the other underutilized resources remain inactive for greater energy savings. This paper presents a fuzzy logic based reconfiguration engine targeted to optimize a multicore architecture according to the workload requirements for optimum balance between power and performance of the system. The proposed fuzzy logic reconfiguration engine is designed around a 16-core SCMP architecture comprising of reconfigurable cache memories, power gated cores and adaptive on-chip network routers for minimizing leakage energy effects for inactive components. A coarse grained architecture was selected for being able to reconfigure faster, thus making it feasible to be used for runtime adaptation schemes. The presented architecture is analyzed over a set of OpenMP based parallel benchmarks and results show significant energy savings in all cases.

Multicore architectures are mainstream due to ever increasing demand of throughput by modern applications. However, the suboptimal utilization of available resources in these architectures may imply an inevitable energy overhead. This energy overhead can only be avoided if the multicore systems support reconfiguration of available resources as per application demand. To achieve the target objectives (i.e., Energy efficiency with Throughput maximization) in multicore systems, many decision variables need to be optimized or analyzed to find the better trade-off. Heuristic-based approaches are aimed to provide a good-enough solution instead of a lengthy exhaustive search. This paper presents an Evolutionary Algorithm (EA)-based approach, i.e., Nondominated Sorting Genetic Algorithm-II (NSGA-II). Three decision variables, i.e., number of cores, cache size and frequency are used to find best solution. The proposed approach is validated over a set of parallel benchmarks using a cycle accurate simulator. The results show a significant amount of energy saving along with minimal impact on the throughput of the system.

The emergence of Multi Processor System on Chip (MPSoC) architectures with reconfigurable options is revolutionizing general purpose processing. Reconfigurable architectures give us the opportunity to allocate system resources with respect to specifi

Modern multicore architectures have an ability to allocate optimum system resources for a specific application to have improved energy and throughput balance. The system resources can be optimized automatically by using optimization algorithms. State-of-the-art using optimization algorithm in the field of such architectures has shown promising results in terms of minimized energy consumption through configuration of number of CPU cores, limited cache sizes and operating frequency. We propose, in this work, a Cat Swarm Optimization (CSO) algorithm-based technique, Integer CSO (ICSO) for the design space exploration (DSE) of multicore computer architectures to find improved energy and throughput balance. The proposed integer variant of CSO algorithm demonstrates convergent behavior for all of design space parameters variations. The Pareto front proposed by ICSO is explored by using various SPLASH-2 benchmarks. Results show significant decrease in energy consumption without affecting throughput severely. Simulation results also validate the use of ICSO in DSE for multicore architectures.