Among many types of batteries, Li-ion and Li-S batteries have been of great interest because of their high energy density, low self-discharge, and non-memory effect, among other aspects. Emerging applications require batteries with higher performance factors, such as capacity and cycling life, which have motivated many research efforts on constructing high-performance anode and cathode materials. Herein, recent research about cathode materials are particularly focused on. Low electron and ion conductivities and poor electrode stability remain great challenges. Three-dimensional (3D) porous nanostructures commonly exhibit unique properties, such as good Li⁺ ion diffusion, short electron transfer pathway, robust mechanical strength, and sufficient space for volume change accommodation during charge/discharge, which make them promising for high-performance cathodes in batteries. A comprehensive summary about some cutting-edge investigations of Li-ion and Li-S battery cathodes is presented. As demonstrative examples, LiCoO₂, LiMn₂O₄, LiFePO₄, V₂O₅, and LiNi_1−x−yCo_xMn_yO₂ in pristine and modified forms with a 3D porous structure for Li-ion batteries are introduced, with a particular focus on their preparation methods. Additionally, S loaded on 3D scaffolds for Li-S batteries is discussed. In addition, the main challenges and potential directions for next generation cathodes have been indicated, which would be beneficial to researchers and engineers developing high-performance electrodes for advanced secondary batteries.

With the increasing complexity of neural network models, the huge communication overhead in federated learning (FL) has become a significant issue. To mitigate resource consumption, incorporating pruning algorithms into federated learning has emerged as a promising approach. However, existing pruning algorithms exhibit high sensitivity to network architectures and typically require multiple sessions of retraining to identify optimal structures. The direct application of such strategies to FL would inevitably introduce an additional communication cost. To this end, we propose a novel communication-efficient federated learning framework, DualPFL (Dual Sparse Pruning Federated Learning), designed to address these issues by implementing dynamic sparse pruning and adaptive model aggregation strategies. The experimental results demonstrate that, compared to similar works, our framework can improve convergence speed by more than two times under non-IID data, achieving up to 84% accuracy on the CIFAR-10 dataset, 95% mean average precision (mAP) on the COCO dataset using YOLOv8, and 96% accuracy on the TT100K traffic sign datasets. These findings indicate that DualPFL facilitates secure and efficient collaborative computing in smart city applications.

Person Re-identification (Re-ID) has great potential in video surveillance and security. At present, Re-ID in the visible light field has reached a relatively high precision, but the related research on infrared-visible cross-modality ReID problem for night monitoring still has plenty of room for improvement. Current methods mainly focus on extracting the features of thermal(infrared) and visible person images using two models, and then classifying and measuring learning through partial sharing weights and the same loss regression layer. We found that the main difference between infrared image and visible light lies in color and edge sharpening. In this paper, we proposed a simple and effective end-to-end crossmodality Re-ID model named cmPCB by using a Part-based Convolution-al Baseline (PCB) model for feature learning. We use Resnet network to extract network features, and we proposed a Multi-Layer Constrained (MLC) Loss, and extend the distance between near infrared and visible modes. Experimental results demonstrate that our model has superi-or performance compared to the state-of-the-arts, i.e. on SYSU- MM01 dataset(All-search multi-shot), Rank1 is improved from 43.86% to 65.83%, mAP is improved from 30.48% to 53.34%; on RegDB dataset, Rank1 is improved from 50.85% to 81.02%, mAP is improved from 48.67% to 78.73%.

The emergence of cyber-physical-social systems (CPSS) as a novel paradigm has revolutionized the relationship between humans, computers and the physical environment. CPSS extend cyber-physical systems (CPS) to include the social domain, which introduces a challenge of massive data processing. As a typically giant CPS, the Five-hundred-meter Aperture Spherical radio Telescope (FAST), the world’s largest filled-aperture radio telescope, generates massive volume of data which poses a huge storage problem that CPSS face likewise and requires real-time data compressing to reduce data storage and movement overhead. The recently introduced Bitshuffle preprocessing algorithm is a novel approach towards exploiting spatial redundancy incorporation to improve the compression ratio with a specific compressor. However, the existing high-performance CPU-based solutions cannot satisfy the performance requirement and power budget requirement simultaneously. In the paper, we propose the implementation of this algorithm on Field Programmable Gate Array (FPGA) and present an unique data transformation strategy to turn raw FAST data in classic FITS format into another format to support huge file sizes, i.e. Hierarchical Data Format (HDF5). Evaluation results show that our implementation can achieve 3.2Gbyte/s throughput which can be equipped with LZ4 compressor to be high performance compressor. This makes Bitshuffle on FPGAs a candidate for meeting the computational and energy efficiency constraints of radio telescopes and provide reference for CPSS facing the same situation.

The SKA (Square Kilometer Array) radio telescope will become the most sensitive telescope by correlating a huge number of antenna nodes to form a vast array of sensors in a region over one hundred kilometers. Faceting, the wide-field imaging algorithm, is a novel approach towards solving image construction from sensing data where earth surface curves cannot be ignored. However, the traditional processor of cloud computing, even if the most sophisticated supercomputer is used, cannot meet the extremely high computation performance requirement. In this paper, we propose the design and implementation of high-efficiency FPGA (Field Programmable Gate Array) -based hardware acceleration of the key algorithm, faceting in SKA by focusing on phase rotation and gridding, which are the most time-consuming phases in the faceting algorithm. Through the analysis of algorithm behavior and bottleneck, we design and optimize the memory architecture and computing logic of the FPGA-based accelerator. The simulation and tests on FPGA are done to confirm the acceleration result of our design and it is shown that the acceleration performance we achieved on phase rotation is 20× the result of the previous work. We then further designed and optimized an efficient microstructure of loop unrolling and pipeline for the gridding accelerator, and the designed system simulation was done to confirm the performance of our structure. The result shows that the acceleration ratio is 5.48 compared to the result tested on software in gridding parts. Hence, our approach enables efficient acceleration of the faceting algorithm on FPGAs with high performance to meet the computational constraints of SKA as a representative vast sensor array.