A distortion-compensated charge transfer amplifier (DCCTA) is proposed to improve the linearity constraints of the differential charge transfer amplifier (DCTA). The proposed DCCTA effectively reduces distortion at its output by source degeneration, cross coupling, and making the drain-to-source voltage of the amplifying transistor independent of the applied input signal. This DCCTA yields an effective number of bits of 9.26 bits, compared with 6.05 bits for the DCTA at 40 MHz while consuming only 13.5 μW from a 1.2-V source. A 1.66-MHz cyclic pipeline analog-to-digital converter employing this DCCTA as a residue amplifier was simulated using 90-nm CMOS process, resulting in a peak resolution of 9.21 bits, without being limited by the thermal noise.

Existing methods used for the clock distribution of multiple dies employ a balanced tree structure to minimize the impact of the within-die process and loading variations. No topology for die-to-die clock skew compensation of more than two dies has been presented yet. This article presents a novel die-to-die clock skew compensation topology to address these limitations. Unlike existing designs, the proposed topology does not need a phase detector (hence, no dead zone); it only requires one through-silicon via (TSV) to connect a pair of dies and one digitally controlled delay line (DCDL) in each die; thus, there is no skew from extra TSVs and DCDLs. Accordingly, the system has a small chip area and low lock time. The postsynthesis of this work was accomplished in a 65-nm CMOS process. The performance of our design was evaluated theoretically and practically in terms of mismatch/finite resolution of delay lines, buffer mismatch, and TSV delay. Under identical conditions, the residual skew of the proposed design was as low as 13 ps at 1 GHz. This study is the first to obtain the solution for die-to-die clock synchronization of multiple dies (more than two dies) in a three-dimensional (3-D) integrated circuit, while other systems can only support two dies.

A highly linear current‐controlled delay unit (CCDU) is presented. The proposed design linearly delays an input clock edge against an applied input current. The topology features a directly proportional input/output relation compared with an inversely proportional one in the traditional current‐starved inverter (CSI). The proposed CCDU features a THD of only 0.15% compared with 22.6% in a conventional CSI over the same input dynamic current range of 180 nA. The proposed CCDU is implemented in 65 nm CMOS and consumes only 0.74 μW. An analogue‐time‐digital ADC is simulated using the proposed CCDU as a front‐end block, achieving a resolution (ENOB) of 9.07 bits. Monte Carlo analysis confirms the linearity of the proposed CCDU under mismatch and process variation.

This brief presents beyond rail-to-rail (BR2R) compliant cascode current sources to markedly improve the compliance voltage and output impedance of the extensively used wide-swing cascode current source. The proposed BR2R sources employ a bootstrapping technique to linearly charge a load capacitor to beyond the supply rails Vdd or gnd while maintaining an improved output impedance over an equivalent wide-swing cascode source. A process and mismatch-insensitive differential voltage-to-time (DVT) converter employing these BR2R sources is fabricated in 65-nm CMOS and occupies 0.021 mm², while dissipating 47 μW at 1 V. The measured BR2R DVT signal to noise and distortion ratio is 50.2 dB, compared to 38.7 dB for the wide-swing cascode-based DVT within a 2-MHz input bandwidth. The DVT achieves a common mode rejection ratio of 35.1 dB for a 0.4-0.6-V input common-mode range.

This manuscript investigates the use of different multi-loop voltage-controlled oscillator (VCO) structures to mitigate single event effects (SEE). The first approach is a three-stage fully differential cross-coupled ring oscillator, designed with current regulation biasing to enhance supply noise rejection. The second is a fully differential current-mode logic (CML) multi-path ring oscillator with coarse/fine control. Both structures were fabricated in 28-nm FDSOI technology. The cross-coupled ring VCO exhibits enhanced performance when using the high-current configuration, showing a phase noise of -80.1 dBc/Hz at 1 MHz offset from the center frequency of 1.49 GHz and a figure of merit (FoM) of 140. Moreover, the CML multi-path VCO stands out as a high-performance structure with -93.4 dBc/Hz phase noise measured at 1 MHz offset from the 1.42 GHz carrier frequency and a FoM of 151. Single event effects (SEE) and total ionizing dose (TID) responses were evaluated using a 105 MeV proton beam and ⁶⁰Co radiation, respectively. Experimental results demonstrated significant single event transient (SET) mitigation with both solutions, with the CML multi-path VCO exhibiting superior radiation tolerance with a maximum single event frequency transient (SEFT) of 4.2% and a maximum recovery time of 1.3 ns. Both designs showed high TID tolerance up to 300 krads.