This article proposes boosting the multiplication performance for convolutional neural network (CNN) inference using a precision prediction preprocessor which controls various precision approximate multipliers. Previously, utilizing approximate multipliers for CNN inference was proposed to enhance the power, speed, and area at a cost of a tolerable drop in the accuracy. Low precision approximate multipliers can achieve massive performance gains; however, utilizing them is not feasible due to the large accuracy loss they cause. To maximize the multiplication performance gains while minimizing the accuracy loss, this article proposes using a tiny two-class precision controller to utilize low and high precision approximate multipliers hybridly. The performance benefits for the proposed concept are presented for multi-core multi-precision architectures and single-core reconfigurable architectures. Additionally, a design for a merged reconfigurable approximate multiplier with two precisions is proposed for utilization in single-core architectures. For performance comparison, several segments-based approximate multipliers with different precisions were synthesized using CMOS 15nm technology. For accuracy evaluation, the concept was simulated on VGG19, Xception, and DenseNet201 using the ImageNetV2 dataset. This article will demonstrate that the proposed concept can achieve significant performance gains with a minimal accuracy loss when compared to designs that utilize exact multipliers or single-precision approximate multipliers.

A Bandgap reference (BGR) circuit with a new high-order curvature-compensation technique is proposed in this paper. The curvature method operates by adding up two correction voltages. The first one is proportional to the difference in gate-source voltages of two MOS transistors ( $\Delta V_{\mathrm {GS}}$ ) operating in weak inversion mode, while the second one ( $V_{\text {NL}}$ ) is generated using a nonlinear current created by a piecewise-linear circuit. To improve the power supply rejection ratio (PSRR) and the line regulation performance, a low-power pre-regulator isolates the circuit power supply and BGR output. Additionally, the chopping technique reduces the output voltage noise and offset. Consequently, the overall PVT robustness of the proposed circuit is significantly improved. The circuit was implemented using a thick-oxide transistor in a standard $0.18 \mathrm {\mu m}$ CMOS technology with a 3.3 V power supply voltage. The silicon results exhibit a temperature coefficient of 5–15 ppm/°C in the temperature range of −10 °C to 110 °C, whereas the simulated results demonstrate a similar performance within the temperature range of −40 °C to 150 °C. The supply current consumption is $150 ~\mu \text{A}$ , and the chip area is $0.56\times0.8$ mm2. The measured peak noise at the output is $1.42 ~\mu \text{V}/\sqrt {\text {Hz}} $ @320 Hz, the measured PSRR @ 1 kHz is −80 dB, and the line regulation performance is 10 ppm/V, making the proposed circuit suitable for applications requiring low noise, high-order temperature compensation, and robust PVT performance.

HEVC (High Efficiency Video Coding) encryption, which has been proposed to encrypt intraprediction modes (structural information), transform coefficients (texture information) and motion related codewords (motion information), has received considerable attention recently. However, there is still the issue of efficiency when HEVC encryption is applied in the Internet of Multimedia Things (IoMT). Aiming at this challenge, in this paper, we propose a new low overhead HEVC encryption scheme for energy-constrained IoMT. Concretely, the proposed scheme adjusts the selection of the aforementioned syntax elements to be encrypted according to the structure, texture and motion energy present in each frame. It works as follows. The energy levels of quantized coefficients and motion vectors are calculated and compared with adaptive threshold values to classify the energy level in each video frame. When there is a high energy frame in the video, all the syntax elements are encrypted. When there is a low energy frame, alternate syntax elements are encrypted for achieving low encryption overhead. Moreover, in the case of transform coefficients, to withstand the interpolation attack, alternate coefficients are encrypted after correlating the frame with its neighboring coefficients. Extensive experiments were conducted, and the results demonstrate that the proposed scheme efficiently reduces the encryption overhead with low impact on the security level, making it suitable for IoMT.

Accuracy evaluation in machine learning is based on the split of data into a training set and a test set. This critical step is applied to develop machine learning models including models based on sensor data. For sensor-based problems, comparing the accuracy of machine learning models using the train/test split provides only a baseline comparison in ideal situations. Such comparisons won’t consider practical production problems that can impact the inference accuracy such as the sensors’ thermal noise, performance with lower inference quantization, and tolerance to sensor failure. Therefore, this paper proposes a set of practical tests that can be applied when comparing the accuracy of machine learning models for sensor-based problems. First, the impact of the sensors’ thermal noise on the models’ inference accuracy was simulated. Machine learning algorithms have different levels of error resilience to thermal noise, as will be presented. Second, the models’ accuracy using lower inference quantization was compared. Lowering inference quantization leads to lowering the analog-to-digital converter (ADC) resolution which is cost-effective in embedded designs. Moreover, in custom designs, analog-to-digital converters’ (ADCs) effective number of bits (ENOB) is usually lower than the ideal number of bits due to various design factors. Therefore, it is practical to compare models’ accuracy using lower inference quantization. Third, the models’ accuracy tolerance to sensor failure was evaluated and compared. For this study, University of California Irvine (UCI) ‘Daily and Sports Activities’ dataset was used to present these practical tests and their impact on model selection.

A comparison of the performance of various machine learning models to predict the direction of a wall following robot is presented in this paper. The models were trained using an open-source dataset that contains 24 ultrasound sensors readings and the corresponding direction for each sample. This dataset was captured using SCITOS G5 mobile robot by placing the sensors on the robot waist. In addition to the full format with 24 sensors per record, the dataset has two simplified formats with 4 and 2 input sensor readings per record. Several control models were proposed previously for this dataset using all three dataset formats. In this paper, two primary research contributions are presented. First, presenting machine learning models with accuracies higher than all previously proposed models for this dataset using all three formats. A perfect solution for the 4 and 2 inputs sensors formats is presented using Decision Tree Classifier by achieving a mean accuracy of 100%. On the other hand, a mean accuracy of 99.82% was achieves using the 24 sensor inputs by employing the Gradient Boost Classifier. Second, presenting a comparative study on the performance of different machine learning and deep learning algorithms on this dataset. Therefore, providing an overall insight on the performance of these algorithms for similar sensor fusion problems. All the models in this paper were evaluated using Monte-Carlo cross-validation.

We focus on a hardware implementation of the concatenated forward error-correction (FEC) decoder defined in 400ZR implementation agreement to provide a throughput of 400 Gbps over fiber-optical communication links. We propose a soft-input hard-output low-complexity decoding algorithm for the inner Hamming code. We demonstrate that the algorithm leads to an efficient hardware design with low silicon area and power dissipation. We then propose a hardware implementation architecture of the outer staircase decoder. It features a highly optimized low-power implementation of Bose-Chaudhuri-Hocquenghem (BCH) component decoders and the staircase decoder memory that can be efficiently accessed by either vertical or horizontal component decoders. Finally, we analyze the hardware implementation of the entire 400ZR decoder and investigate the trade-off in terms of power, area, and speed, that results from the inner/outer decoder concatenation and is dictated by the bit-error rate at the output of the inner decoder.