In this brief, two novel diode-triggered silicon-controlled rectifiers (DTSCRs) with fast turn-on speed have been presented. By embedding current gain amplifier modules (i.e., Sziklai pair and Darlington pair) into the conventional DTSCR, the current gain of parasitic bipolar junction transistors (BJTs) on the silicon-controlled rectifier (SCR) path in the new devices becomes much larger than that of the conventional counterpart, thus resulting in a faster turn-on speed and better quasi-static ${I}$ – ${V}$ characteristics. As such, the quasi-static triggering characteristic of the new DTSCR improves by 80%, and the turn-on speed improves by 42%–93% for different current levels.

In this article, a robust high-holding voltage silicon-controlled rectifier (HHSCR) is implemented and realized in a 0.18- $\mu \text{m}$ BCD process for on-chip electrostatic discharge (ESD) protection. The proposed HHSCR was constructed by embedding a NMOSFET in the p-well of a modified lateral silicon-controlled rectifier (MLSCR). Benefiting from the shunting effect of the embedded NMOSFET path, the proposed HHSCR achieved a high-holding voltage with a relatively high robustness. Transmission line pulse (TLP) test results show that the proposed HHSCR exhibits a high-holding voltage of 11.6 V and a failure current ( ${I}_{\text {t2}}{)}$ of 1.59 A at a finger width of 50 $\mu \text{m}$ . Furthermore, the internal physical mechanism of the proposed HHSCR was explored by technology computer-aided design (TCAD) simulation.

In this paper, an enhanced modified lateral silicon-controlled rectifier (EMLSCR) has been proposed and demonstrated. Compared with the traditional MLSCR, the EMLSCR possesses a lower trigger voltage of 7.0 V as well as a higher robustness, making it very suitable for the electrostatic discharge (ESD) protection for 2.5-V/3.3-V/5-V IOs in the advanced 65-nm epitaxial CMOS technology. Additionally, an improved transmission line pulsing (TLP) measurement strategy by adopting TLP pulses with various rise time has been put forward to provide a convenient and economical approach to explore the conduction uniformity of the ESD device for the first time. Furthermore, two optimization methods are proposed and evaluated to overcome the prefailure issue due to the small well resistance inherited in the EPI process as well. The method of well pickup segmentation is demonstrated to be more efficient since it could increase the well resistance and augment the effective emitter area of parasitic bipolar junction transistors (BJTs) under constant device area.

Gate-grounded n-channel MOSFET (GGNMOS) has been widely used in electrostatic discharge (ESD) protection applications. In this letter, an enhanced GGNMOS, called the EGGNMOS, is proposed and demonstrated. The new device has the same topology as the conventional GGNMOS, except that a few P+ regions are being added to the N+ guard ring (NGR). This novel approach enables the formation of parasitic silicon-controlled rectifiers (SCR’s), thus resulting in a much higher current handling capability in the EGGNMOS than the GGNMOS under the same silicon footprint. Our experimental results indicate that the proposed EGGNMOS, with an ESD design window suitable for 5V CMOS technologies, could achieve an ESD failure current density 8 time higher that the GGNMOS. Moreover, the transient overshoot characteristic of EGGNMOS is comparable with that of GGNMOS. Three-dimensional TCAD simulation has also been carried out to verify that the NGR isolation functionality of EGGNMOS is not being comprised.